View 325119-001_5104012.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

reference number: 325119-001 intel? xeon? processor e7- 8800/4800/2800 product families datasheet volume 1 of 2 april 2011
2 datasheet volume 1 of 2 l information in this document is provided in conne ction with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual proper ty rights is granted by this document. except as provided in intel's terms and condit ions of sale for such products, in tel assumes no liability whatsoever, and intel disclaims any express or implied warranty, rela ting to sale and/or use of intel products including liability or warranties relating to fitness for a particul ar purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical cont rol or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. the intel? xeon? processor e7-8800/4800/2800 product families may contain design defects or e rrors known as errata, which may cause the product to deviate from published specificatio ns. current characterized errata are available upon request. throughout this document, intel? xeon? processor e7-8800/4800/ 2800 product families will be referred to as the intel? xeon? e7-8800/4800/2800 product families processor when us ed in referring to a singular processor. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsib ility whatsoever for conflicts or incompatibilities arising fro m future changes to them. the information here is subject to change without notice. do not finalize a design with this information. contact your local intel sales office or your distributor to obta in the latest specifications an d before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature, may be obtained by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com/design/literature.htm 64-bit computing on intel architectu re requires a computer system with a processor, chipset, bios, operating system, device drivers and applicatio ns enabled for intel ? 64 architecture. performance will vary de pending on your hardware and software configurations. consult with your system vendor fo r more information. for more information, visit http://www.intel.com/info/em64t . intel? aes-ni requires a computer system with an aes-ni enabled processor, as well as non-intel software to execute the instructions in the correct sequ ence. aes-ni is available on select intel? pr ocessors. for availability, consult your reselle r or system manufacturer. for more information, see http://softwar e.intel.com/en-us/articles/intel-advanced-encryption-standard- instructions-aes-ni/ enhanced intel speedstep technology: see the processor spec find er at http://ark.intel.com or contact your intel representative for more information. enabling execute disable bit functionality re quires a pc with a processor with execut e disable bit capability and a supporting operating system. check with your pc manufacturer to determine whether your system delivers this functionality. for more information, visit http://www.intel.com/technology/xdbit/index.htm intel? virtualization technology requires a computer system with an enabled intel? processor, bios, virtual machine monitor (vmm) and for some uses, certain computer sy stem software enabled for it. functionalit y, performance or other benefits will var y depending on hardware and software configurations and may requir e a bios update. software applications may not be compatible with all operating systems. please check with your application vendor. intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor family , not across different processor families. go to: http://www.intel.com/products/processor_number intel? turbo boost technology requires a pc with a processor with intel? turbo boost techno logy capability. intel turbo boost technology performance varies depending on hardware, software and system configuration. consult your pc manufacturer on whether your system delivers intel turbo bo ost technology. for more information, visit http://www.intel.com/technology/turboboost intel, intel xeon, the intel logo and intel speedstep are trademarks or registered trademarks of intel co rporation in the unite d states and other countries. i 2 c is a two-wire communications bus/protocol de veloped by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses from various entities, including philips electronics n.v. and north american ph ilips corporation. *other names and brands may be cl aimed as the property of others. copyright ? 2011, intel corpor ation. all rights reserved.
datasheet volume 1 of 2 3 contents 1introduction .............................................................................................................. 9 1.1 terminology ....................................................................................................... 9 1.2 references ....................................................................................................... 11 1.3 state of data .................................................................................................... 11 1.4 statement of volatility ........... ........... .......... ........... ........... ............ ......... ............ 11 2 electrical specifications ........................................................................................... 13 2.1 processor maximum ratings ............................................................................... 13 2.2 socket voltage identification............................................................................... 14 2.3 signal groups ................................................................................................... 19 2.4 processor dc specifications ................................................................................ 21 2.5 intel ? qpi and intel ? scalable memory interconnect (intel ? smi) interface differential signaling ............................................................................ 26 2.5.1 intel qpi signaling specifications ............................................................. 27 2.5.2 intel qpi electrical specifications .......... .................................................... 30 2.5.3 intel smi signaling specifications ............................................................. 34 2.5.4 intel smi transmitter and receiver specifications ....................................... 34 2.6 platform environmental control interface (peci) dc specifications........................... 40 2.6.1 dc characteristics .................................................................................. 41 2.6.2 input device hysteresis .......................................................................... 41 2.7 dc specifications .............................................................................................. 42 2.8 ac specifications............................................................................................... 43 2.9 processor ac timing waveforms ......................................................................... 49 2.10 flexible motherboard guidelines .......................................................................... 55 2.11 reserved (rsvd) or unused signals .................................................................... 55 2.12 test access port connection ............................................................................... 55 2.13 mixing processors.............................................................................................. 55 2.14 processor spd interface ..................................................................................... 55 3 processor package mechanical specifications .......................................................... 57 3.1 package mechanical specifications ................ ....................................................... 57 3.1.1 package mechanical drawing.................................................................... 58 3.1.2 processor component keep-out zones ...................................................... 61 3.1.3 package loading specifications ................................................................ 61 3.1.4 package handling guidelines.................................................................... 61 3.1.5 package insertion specifications............................................................... 61 3.1.6 processor mass specification .................................................................... 62 3.1.7 processor materials................................................................................. 62 3.1.8 processor markings................................................................................. 62 3.1.9 processor land coordinates ..................................................................... 63 4 pin listing ............................................................................................................... 65 4.1 processor package bottom land assignments........................................................ 65 4.1.1 processor pin list, sorted by socket name ................................................ 65 4.1.2 processor pin list, sorted by land number ................................................ 85 5 signal definitions .................................................................................................. 105 6 thermal specifications .......................................................................................... 111 6.1 package thermal specifications ......................................................................... 111 6.1.1 thermal specifications .......................................................................... 111 6.1.2 thermal metrology ............................................................................... 117 6.2 processor thermal features .............................................................................. 118 6.2.1 thermal monitor features...................................................................... 118 6.2.2 intel ? thermal monitor 1 ...................................................................... 118
4 datasheet volume 1 of 2 6.2.3 intel thermal monitor 2 ......................................................................... 118 6.2.4 on-demand mode ................................................................................. 119 6.2.5 prochot_n signal ............................................................................... 120 6.2.6 force_pr_n signal .............................................................................. 120 6.2.7 thermtrip_n signal ............................................................................ 121 6.2.8 thermalert_n signal .......................................................................... 121 6.3 platform environment control interface (peci) .................................................... 121 6.3.1 peci client capabilities....... ............ ........... ............ ........... ........ ............. 122 6.3.2 client command suite ........................................................................... 123 6.3.3 multi-domain commands ....................................................................... 138 6.3.4 client responses .................................................................................. 138 6.3.5 originator responses ............................................................................ 139 6.3.6 temperature data ................................................................................ 140 6.3.7 client management ............................................................................... 141 7features ................................................................................................................ 145 7.1 introduction .................................................................................................... 145 7.2 clock control and low power states ................................................................... 146 7.2.1 processor c-state power spec ifications .................................................... 146 7.3 sideband access to processor information rom via smbus .................................... 146 7.3.1 processor information rom .................................................................... 146 7.3.2 scratch eeprom ................................................................................... 148 7.3.3 pirom and scratch eeprom supported smbus transactions....................... 149 7.4 smbus memory component addressing............................................................... 149 7.5 managing data in the pirom ............................................................................. 150 7.5.1 header ................................................................................................ 150 7.5.2 processor data ..................................................................................... 154 7.5.3 processor core data.............................................................................. 156 7.5.4 processor uncore data .......................................................................... 159 7.5.5 package data ....................................................................................... 164 7.5.6 part number data................................................................................. 165 7.5.7 thermal reference data ........................................................................ 168 7.5.8 feature data ........................................................................................ 169 7.5.9 other data .......................................................................................... 171 7.5.10 checksums .......................................................................................... 172 8 debug tools specifications .................................................................................... 173 8.1 logic analyzer interface ................................................................................... 173 8.1.1 mechanical considerations ..................... ................................................ 173 8.1.2 electrical considerations ........................ ................................................ 173
datasheet volume 1 of 2 5 figures 2-1 vcc static and transient tolerance .............. ....................................................... 24 2-2 vcache static and transient tolerance ............. .................................................... 25 2-3 overshoot example waveform ............................................................................ 26 2-4 active odt for a differential link example ............................................................ 26 2-5 validation topology for testing specifications of the reference clock ....................... 27 2-6 differential waveform measurement points ......... .................................................. 27 2-7 setup for validating standalone tx voltage and timing parameters.......................... 28 2-8 setup for validating tx + worst-case interconnect specifications ............................ 29 2-9 required receiver input eye (differential) showing minimum voltage specs ............. 39 2-10 input device hysteresis ..................................................................................... 42 2-11 reset_n setup/hold time for deterministic reset_n deassertion .......................... 45 2-12 thermtrip_n power down sequence .................................................................. 45 2-13 vid step times................................................................................................. 46 2-14 smbus timing waveform.................................................................................... 47 2-15 smbus valid delay timing waveform ................................................................... 47 2-16 flashrom timing waveform.............................................................................. 48 2-17 tap valid delay timing waveform ....................................................................... 48 2-18 test reset (trst_n), force_pr_n , reset_n and prochot_n pulse width waveform ........................................................................................................ 49 2-19 intel qpi system interface electrical test setup for validating standalone tx voltage and timing parameters ...................................................... 49 2-20 intel qpi system interface electrical test setup for validating tx + worst-case interconnect specifications ...... .................................................. 50 2-21 differential clock waveform................................................................................ 50 2-22 differential clock crosspoint specification...... ....................................................... 51 2-23 system common clock valid delay timing wave form ............................................ 51 2-24 differential measurement point for ringback ......................................................... 51 2-25 differential measurement points for rise and fa ll time............................................ 52 2-26 single-ended measurement points for absolute cross point and swing...................... 52 2-27 single-ended measurement points for delta cross point.......................................... 52 2-28 voltage sequence timing requirements ............................................................... 53 2-29 vid step times and vcc waveforms .................................................................... 54 3-1 processor package assembly sketch .................................................................... 57 3-2 processor package drawing (sheet 1 of 2) ............................................................ 59 3-3 processor package drawing (sheet 2 of 2) ............................................................ 60 3-4 processor top-side markings .............................................................................. 62 3-5 processor land coordinates and quadrants, top view ............................................ 63 6-1 130w tdp processor thermal profile .................................................................. 113 6-2 105w tdp processor thermal profile .................................................................. 114 6-3 95w tdp processor thermal profile.................................................................... 116 6-4 case temperature (tcase) measurement location .............................................. 117 6-5 intel? thermal monitor 2 frequency and voltag e ordering ................................... 119 6-6 ping() ............................................................................................................ 123 6-7 ping() example ............................................................................................... 123 6-8 getdib() ........................................................................................................ 124 6-9 device info field definition ........................ ....................................................... 124 6-10 revision number definition........................ ....................................................... 125 6-11 gettemp() ..................................................................................................... 125 6-12 gettemp() example......................................................................................... 126 6-13 pci configuration address ................................................................................ 126 6-14 pciconfigrd()................................................................................................. 127
6 datasheet volume 1 of 2 6-15 pciconfigwr() ................................................................................................. 128 6-16 thermal status word ....................................................................................... 131 6-17 thermal data configuration register .............. .................................................... 132 6-18 acpi t-state throttling control read / write de finition ......................................... 133 6-19 mbxsend() command data format .................................................................... 134 6-20 mbxsend()...................................................................................................... 135 6-21 mbxget()........................................................................................................ 136 6-22 temperature sensor data format .................. .................................................... 140 6-23 peci power-up timeline.................................................................................... 142 7-1 logical schematic of intel ? xeon ? processor e7-8800/4800/2800 product families package............. ............ ........... ............ ........... .......... ............. 145 tables 1-1 references........................................................................................................11 2-1 processor absolute maximum ratings ...................................................................13 2-2 voltage identification definition ...........................................................................15 2-3 signal groups ...................................................................................................20 2-4 signals with rtt ................................................................................................21 2-5 voltage and current specifications ................ .......................................................21 2-6 processor vcc static and transient tolerance.... .....................................................23 2-7 processor vcccache static and transient tolerance ................................................24 2-8 vcc and vcache overshoot specification ...............................................................25 2-9 system clock specifications ......................... .......................................................27 2-10 link speed independent specifications .................................................................29 2-11 clock frequency table........................................................................................30 2-12 parameter values for intel? qpi phy1 channel at 1/4 refclk frequency ...................31 2-13 parameter values for intel qpi channel at 4.8 gt/s................................................32 2-14 parameter values for intel qpi at 6.4 gt/s............................................................33 2-15 parameter values for intel smi at 6.4 gt/s and lower .............................................35 2-16 pll specification for tx and rx ...........................................................................36 2-17 transmitter voltage swing ..................................................................................37 2-18 transmitter de-emphasis (swing setting 110: large) .............................................37 2-19 transmitter de-emphasis (swing setting 100: medium)..........................................37 2-20 transmitter de-emphasis (swing setting 010: small) .............................................37 2-21 summary of differential transmitter output sp ecifications ......................................38 2-22 summary of differential receiver input specific ations.............................................39 2-23 peci dc electrical limits.......................... ...........................................................41 2-24 tap, strap pins, error, powerup, reset, thermal, vid signal group dc specifications ....................................................................................................42 2-25 miscellaneous dc specifications ...........................................................................43 2-26 system reference clock ac specifications........ .....................................................43 2-27 miscellaneous gtl ac specifications .....................................................................44 2-28 vid signal group ac specifications ................ ......................................................45 2-29 smbus and spdbus signal group ac timing sp ecifications ......................................46 2-30 flashrom signal group ac timing specificatio ns..................................................47 2-31 tap signal group ac timing sp ecifications ............................................................48 3-1 processor loading specifications ..........................................................................61 3-2 package handling guidelines ...............................................................................61 3-3 processor materials ............................................................................................62 3-4 mark content ....................................................................................................62 4-1 pin list, sorted by socket name ................... .......................................................65
datasheet volume 1 of 2 7 4-2 pin list, sorted by land number .......................................................................... 85 5-1 signal definitions ............................................................................................ 105 6-1 processor thermal specifications ....................................................................... 112 6-2 130w tdp processor thermal profile table ......................................................... 113 6-3 105w tdp processor thermal profile table ......................................................... 115 6-4 95w tdp processor thermal profile table ........................................................... 116 6-5 summary of processor-specific peci commands ... ............................................... 122 6-6 gettemp() response definition ......................................................................... 126 6-7 pciconfigrd() response definition .................................................................... 127 6-8 pciconfigwr() response definition .................................................................... 129 6-9 mailbox command summary ............................................................................ 129 6-10 counter definition ........................................................................................... 131 6-11 acpi t-state duty cycle definition ................ ..................................................... 132 6-12 mbxsend() response definition ......................................................................... 135 6-13 mbxget() response definition ........................................................................... 136 6-14 domain id definition ....................................................................................... 138 6-15 multi-domain command code reference ............................................................ 138 6-16 completion code pass/fail mask........................................................................ 139 6-17 device specific completion code (cc) definiti on.................................................. 139 6-18 originator response guidelines ......................................................................... 140 6-19 error codes and descriptions ............................................................................ 141 6-20 peci client response during power-up (during ?data not ready?) ......................... 141 6-21 power impact of peci commands vs. c-states .. .................................................. 143 6-22 peci client response during s1 ........................................................................ 143 7-1 processor c-state power specifications .............................................................. 146 7-2 read byte smbus packet .................................................................................. 149 7-3 write byte smbus packet ................................................................................. 149 7-4 memory device smbus addressing..................................................................... 150 7-5 128-byte rom checksum values ....................................................................... 172
8 datasheet volume 1 of 2 revision history document number revision number description date 325119 001 ? public release april 2011
datasheet volume 1 of 2 9 introduction 1 introduction the intel ? xeon ? processor e7-8800/4800/2800 product families are a next- generation intel ? xeon ? multi-core mp family processor. the processor uses intel ? quickpath interconnect (intel ? qpi) technology, implementing up to four high-speed serial point-to-point links. it is optimized fo r mp configurations targeted at enterprise and technical computing applications, delivering server-class ras and performance. intel xeon processor e7-8800/4800/2800 product families are multi-core processors, based on 32-nm process technology. the processors feature intel quickpath interconnect point-to-point links capable of up to 6.4 gt/s, up to 30 mb of shared cache, and an integrated memory controller. the processors support all the existing streaming simd extensions 2 (sse2), st reaming simd extensions 3 (sse3) and streaming simd extensions 4 (sse4). the processors support several advanced technologies: execute disable bit, intel ? 64 technology, enhanced intel speedstep ? technology, intel ? virtualization technology (intel ? vt), and simultaneous multi- threading. 1.1 terminology a ?_n? after a signal name refers to an active low signal, indicating that a signal is in the asserted state when driven to a low level. for example, when reset_n is low (that is, when reset_n is asserted), a reset has been requested. conversely, when tck is high (that is, when tck is asserted), a test clock request has occurred. ? enhanced intel speedstep technology ? enhanced intel speedstep technology allows the o/s to reduce power consumption when performance is not needed. ? eye definitions ? the eye at any point along the data channel is defined to be the creation of overlapping of a large number of ui of the data signal and timing width measured with regards to the edges of a se parate clock signal at any other point. each differential signal pair by combining the d+ and d- signals produces a signal eye. a _dn and _dp after a signal na me refers to a differential pair. ? fclga-1567 ? the intel xeon processor e7-8800/4800/2800 product families are available in a flip-chip land grid ar ray (fc-lga) package, consisting of 10 processor cores mounted on a pinned substr ate with an integrated heat spreader (ihs). ? functional operation ? refers to the normal operating conditions in which all processor specifications, including dc, ac, system bus, signal quality, mechanical, and thermal, are satisfied. feature intel ? xeon ? processor e7-8800/4800/2800 product families cache sizes instruction cache (l1) = 32 kb/core (i) and16 kb/core (d) data cache (l2) = 256 kb/core last level cache (l3) = 30 mb shared among cores data transfer rate up to four full-width intel qu ickpath interconnect links, up to 6.4 gt/s in each direction multi-core support up to 10 cores per processor multiple processor support dependent on sku, and supporting silicon. minimum of two cpus. package 1567-land fclga
introduction 10 ? integrated heat spreader (ihs) ? a component of the processor package used to enhance the thermal performance of the package. component thermal solutions interface with the processor at the ihs surface. ? intel ? quickpath interconnect (intel ? qpi) ? intel quickpath interconnect is a cache-coherent, links-based inte rconnect specification for intel ? processor, chipset, and i/o bridge components. ? jitter ? any timing variation of a transition edge or edges from the defined ui. ? mp ? multi-processor system consisting of more than two processors. ? oem ? original equipment manufacturer. ? processor information rom (pirom) ? a memory device located on the processor and accessible via the system management bus (smbus) which contains information regarding the processor?s features. this device is shared with the scratch eeprom, is programmed during manufacturing, and is write-protected. ? scratch eeprom (electrically erasable, programmable read-only memory) ? a memory device located on the processor and addressable via the smbus which can be used by the oem to store information useful for system management. ? smbus ? system management bus. a two-wire interface through which simple system and power management related devices can communicate with the rest of the system. it is based on the principals of the operation of the i 2 c* two-wire serial bus developed by phillips semiconductor. smbus is a subset of the i 2 c bus/protocol developed by intel. implementations of the i 2 c bus/protocol or the smbus bus/ protocol may require licensing from various entities, including, but not restricted to, philips electronics n.v. and north american philips corporation. ? storage conditions ? refers to a non-operational state. the processor may be installed in a platform, in a tray, or loose. processors may be sealed in packaging or exposed to free air. under these conditions, processor pins should not be connected to any supply voltages, have any i/os biased, or receive any clocks. ? intel ? xeon ? processor e7-8800/48 00/2800 product familie s ? the entire product, including processor core, die, substrate and integrated heat spreader (ihs). ? unit interval (ui) ? intel qpi signaling convention is binary and unidirectional. in this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. if a number of edges are collected at instances t 1 , t 2 , t n ,...., t k then the ui at instance ?n? is defined as: ui n = t n - t n - 1
datasheet volume 1 of 2 11 introduction 1.2 references material and concepts available in the fo llowing documents may be beneficial when reading this document: notes: 1. document is available publicly at http://developer.intel.com . 1.3 state of data the data contained within this document is production data. 1.4 statement of volatility no intel? xeon? e7-8800/4800/2800 product families processors retain any end user data when powered down and/or when the parts are physically removed from the socket. table 1-1. references document location notes intel ? xeon ? processor e7-8800/4800/2800 product families datasheet volume 2 of 2 325120 1 ap-485, intel ? processor identification and the cpuid instruction 241618 1 intel ? 64 and ia-32 architecture software developer's manual volume 1: basic architecture volume 2a: instruction set reference, a-m volume 2b: instruction set reference, n-z volume 3a: system programming guide, part 1 volume 3b: systems programming guide, part 2 253665 253666 253667 253668 253669 1 intel ? 64 and ia-32 architectures optimization reference manual 248966 1 intel ? virtualization technology specification for directed i/o architecture specification d51397-001 1 voltage regulator module (vrm) an d enterprise voltage regulator- down (evrd) 11.1 design guidelines 321736 1
introduction 12
datasheet volume 1 of 2 13 electrical specifications 2 electrical specifications the intel xeon processor e7-8800/4800/2800 product families package pin electrical specification is outlined in this section. the intel xeon e7-8800/4800/2800 product families processor interfaces to other comp onents of the platform via connections established at intel ? quickpath interconnect (intel ? qpi), intel ? scalable memory interconnect (intel ? smi), system management interfaces, power, reset, clock and debug signals. the electrical characteristics of all such signals, categorized per the i/o type, are documented in this section. 2.1 processor maximum ratings ta b l e 2 - 1 specifies absolute maximum and minimum ratings. within operational maximum and minimum limits, functionality and long-term reliability can be expected. processor maximum ratings outlined in ta b l e 2 - 1 are applicable for all intel xeon e7- 8800/4800/2800 product families processor skus. at conditions outside operational maximum ratings, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. if a device is returned to conditions within operational maximum and minimum ratings after having been subjected to conditions ou tside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to condit ions exceeding the functional operation condition limits. at conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. moreover, if a device is subjected to these conditions for any length of time, then when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded. although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields. table 2-1. processor absolute maximum ratings (sheet 1 of 2) symbol parameter min max unit notes 1, 2 vcc processor core supply voltage with respect to v ss ?0.3 1.42 v v cache processor cache voltage with respect to v ss ?0.3 1.55 v v reg processor analog supply voltage with respect to v ss ?0.3 1.89 v v ioc processor intel qpi i/o supply voltage with respect to v ss ?0.3 1.55 v v iof processor i/o supply voltage for smi with respect to v ss ?0.3 1.55 v v cc33 processor 3.3v supp ly voltage with respect to v ss 3.135 3.465 v
electrical specifications 14 datasheet volume 1 of 2 notes: 1. for functional operation, all processor electrical, sign al quality, mechanical, and thermal specifications must be satisfied. 2. excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. storage temperature is applicable to storage conditions only. in this scenario, the processor must not receive a clock, and no pins can be connected to a voltage bias. storage within these limits will not affect the long-term reliability of the device. for functional operation, please refe r to the processor case temperature specifications. 4. this rating applies to the processor and does not include any packaging or trays. 2.2 socket voltage identification the vid[7:0], cvid[7:1], and vio_vid[4:1] pi ns identify encoding that determine the voltage to be supplied by the vr to the socket vcore, vcache and vio (the core, cache & system interface voltages for the intel xeon processor e7-8800/4800/2800 product families processor) voltage regulators. the corevid and cachevid specifications for the intel xeon processor e7-8800/4800/2800 product families processors are defined by vr 11.1. vio_vid specifications for the intel xeon processor e7-8800/4800/2800 product families processors are defined by vr 11.0. for corevid and cachevid, individual processor vid values may be calibrated during manufacturing such that two devices at the same core speed may have different default vid settings. furthermore, any intel xeon processor e7-8800/4800/2800 product families processor can drive different vid settings during normal operation. for vio_vid, all processors of a given stepping will have the same values. the voltage identification (vid) specification for the intel xeon processor e7-8800/ 4800/2800 product families processor is defined by the voltage regulator module (vrm) and enterprise voltage regulato r-down (evrd) 11.1 design guidelines . the voltage set by the vid signals is the referenc e vr output voltage to be delivered to the processor vcc pins. vid signals are cmos push/pull drivers. please refer to ta b l e 2 - 2 4 for the dc specifications for these sign als. a voltage range is provided in ta b l e 2 - 5 and changes with frequency. the specifications have been set such that one voltage regulator can operate with all supported frequencies. the intel xeon processor e7-8800/4800/2800 product families processor uses eight voltage identification signals, vid[7:0], to support automatic selection of power supply voltages. ta b l e 2 - 2 specifies the voltage level corresponding to the state of vid[7:0]. a ?1? in this table refers to a high voltage level and a ?0? refers to a low voltage level. if the processor socket is empty (sktocc# high), or the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself. see the voltage regulator module (vrm) and enterp rise voltage regulator-down (evrd) 11.1 design guidelines for further details. the intel xeon processor e7-8800/4800/2800 product families processor provides the ability to operate while transitioning to an adjacent vid and its associated processor core voltage (vcc). this will represent a dc shif t in the load line. it should be noted that a low-to-high or high-to-low voltage state change may result in as many vid transitions as necessary to reach the target core voltage. transitions above the v(isense) analog input voltage with respect to vss for sensing current consumption -0.25 1.15 v t case processor case temperature see chapter 6 see chapter 6 t storage processor storage temperature ?40 85 c 3, 4 table 2-1. processor absolute ma ximum ratings (sheet 2 of 2) symbol parameter min max unit notes 1, 2
datasheet volume 1 of 2 15 electrical specifications maximum specified vid are not permitted. ta b l e 2 - 5 includes vid step sizes and dc shift ranges. minimum and maximum voltages must be maintained as shown in ta b l e 2 - 6 . the vrm or evrd utilized must be capable of regulating its output to the value defined by the new vid. dc specifications for dynamic vid transitions are included in ta b l e 2 - 5 and ta b l e 2 - 6 , while ac specifications are included in ta b l e 2 - 2 8 . refer to the voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 11.1 design guidelines for further details. the vio_vid[4:1] pins identify encoding th at determine the voltage to be supplied by the vr 11.1 to the socket vio voltage regulators. in all cases, when reading from ta b l e 2 - 2 , assume vid7=0, vid6=1, vid5=0, and vid0=0. note that all intel xeon processor e7-8800/4800/2800 product families processor skus will have the same setting. power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable. table 2-2. voltage identificati on definition (sheet 1 of 5) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v cc_max 000000 0 0 off 000000 0 1 off 000000 1 01. 60000 000000 1 11. 59375 000001 0 01. 58750 000001 0 11. 58125 000001 1 01. 57500 000001 1 1 1.56875 000010 0 0 1.56250 0 0 0 0 1 0 0 1 1.55625 0 0 0 0 1 0 1 0 1.55000 0 0 0 0 1 0 1 1 1.54375 000011 0 01. 53750 000011 0 11. 53125 000011 1 01. 52500 000011 1 11. 51875 000100 0 01. 51250 000100 0 11. 50625 000100 1 01. 50000 000100 1 11. 49375 000101 0 01. 48750 000101 0 11. 48125 000101 1 01. 47500 000101 1 11. 46875 000110 0 01. 46250 000110 0 11. 45625 000110 1 01. 45000
electrical specifications 16 datasheet volume 1 of 2 000110 1 11. 44375 000111 0 01. 43750 000111 0 11. 43125 000111 1 01. 42500 000111 1 11. 41875 001000 0 01. 41250 001000 0 11. 40625 001000 1 01. 40000 001000 1 11. 39375 001001 0 01. 38750 001001 0 11. 38125 001001 1 01. 37500 001001 1 11. 36875 001010 0 01. 36250 001010 0 11. 35625 0 0 1 0 1 0 1 0 1.35000 0 0 1 0 1 0 1 1 1.34375 0 0 1 0 1 1 0 0 1.33750 0 0 1 0 1 1 0 1 1.33125 0 0 1 0 1 1 1 0 1.32500 0 0 1 0 1 1 1 1 1.31875 0 0 1 1 0 0 0 0 1.31250 0 0 1 1 0 0 0 1 1.30625 0 0 1 1 0 0 1 0 1.30000 0 0 1 1 0 0 1 1 1.29375 0 0 1 1 0 1 0 0 1.28750 0 0 1 1 0 1 0 1 1.28125 0 0 1 1 0 1 1 0 1.27500 0 0 1 1 0 1 1 1 1.26875 0 0 1 1 1 0 0 0 1.26250 0 0 1 1 1 0 0 1 1.25625 0 0 1 1 1 0 1 0 1.25000 0 0 1 1 1 0 1 1 1.24375 0 0 1 1 1 1 0 0 1.23750 0 0 1 1 1 1 0 1 1.23125 0 0 1 1 1 1 1 0 1.22500 0 0 1 1 1 1 1 1 1.21875 0 1 0 0 0 0 0 0 1.21250 0 1 0 0 0 0 0 1 1.20625 0 1 0 0 0 0 1 0 1.20000 0 1 0 0 0 0 1 1 1.19375 0 1 0 0 0 1 0 0 1.18750 table 2-2. voltage identification definition (sheet 2 of 5) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v cc_max
datasheet volume 1 of 2 17 electrical specifications 0 1 0 0 0 1 0 1 1.18125 0 1 0 0 0 1 1 0 1.17500 0 1 0 0 0 1 1 1 1.16875 0 1 0 0 1 0 0 0 1.16250 0 1 0 0 1 0 0 1 1.15625 0 1 0 0 1 0 1 0 1.15000 0 1 0 0 1 0 1 1 1.14375 0 1 0 0 1 1 0 0 1.13750 0 1 0 0 1 1 0 1 1.13125 0 1 0 0 1 1 1 0 1.12500 0 1 0 0 1 1 1 1 1.11875 0 1 0 1 0 0 0 0 1.11250 0 1 0 1 0 0 0 1 1.10625 0 1 0 1 0 0 1 0 1.10000 0 1 0 1 0 0 1 1 1.09375 0 1 0 1 0 1 0 0 1.08750 0 1 0 1 0 1 0 1 1.08125 0 1 0 1 0 1 1 0 1.07500 0 1 0 1 0 1 1 1 1.06875 0 1 0 1 1 0 0 0 1.06250 0 1 0 1 1 0 0 1 1.05625 0 1 0 1 1 0 1 0 1.05000 0 1 0 1 1 0 1 1 1.04375 0 1 0 1 1 1 0 0 1.03750 0 1 0 1 1 1 0 1 1.03125 0 1 0 1 1 1 1 0 1.02500 0 1 0 1 1 1 1 1 1.01875 0 1 1 0 0 0 0 0 1.01250 0 1 1 0 0 0 0 1 1.00625 0 1 1 0 0 0 1 0 1.00000 0 1 1 0 0 0 1 1 0.99375 0 1 1 0 0 1 0 0 0.98750 0 1 1 0 0 1 0 1 0.98125 0 1 1 0 0 1 1 0 0.97500 0 1 1 0 0 1 1 1 0.96875 0 1 1 0 1 0 0 0 0.96250 0 1 1 0 1 0 0 1 0.95625 0 1 1 0 1 0 1 0 0.95000 0 1 1 0 1 0 1 1 0.94375 0 1 1 0 1 1 0 0 0.93750 0 1 1 0 1 1 0 1 0.93125 0 1 1 0 1 1 1 0 0.92500 table 2-2. voltage identificati on definition (sheet 3 of 5) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v cc_max
electrical specifications 18 datasheet volume 1 of 2 0 1 1 0 1 1 1 1 0.91875 0 1 1 1 0 0 0 0 0.91250 0 1 1 1 0 0 0 1 0.90625 0 1 1 1 0 0 1 0 0.90000 0 1 1 1 0 0 1 1 0.89375 0 1 1 1 0 1 0 0 0.88750 0 1 1 1 0 1 0 1 0.88125 0 1 1 1 0 1 1 0 0.87500 0 1 1 1 0 1 1 1 0.86875 0 1 1 1 1 0 0 0 0.86250 0 1 1 1 1 0 0 1 0.85625 0 1 1 1 1 0 1 0 0.85000 0 1 1 1 1 0 1 1 0.84375 0 1 1 1 1 1 0 0 0.83750 0 1 1 1 1 1 0 1 0.83125 0 1 1 1 1 1 1 0 0.82500 0 1 1 1 1 1 1 1 0.81875 1 0 0 0 0 0 0 0 0.81250 1 0 0 0 0 0 0 1 0.80625 1 0 0 0 0 0 1 0 0.80000 1 0 0 0 0 0 1 1 0.79375 1 0 0 0 0 1 0 0 0.78750 1 0 0 0 0 1 0 1 0.78125 1 0 0 0 0 1 1 0 0.77500 1 0 0 0 0 1 1 1 0.76875 1 0 0 0 1 0 0 0 0.76250 1 0 0 0 1 0 0 1 0.75625 1 0 0 0 1 0 1 0 0.75000 1 0 0 0 1 0 1 1 0.74375 1 0 0 0 1 1 0 0 0.73750 1 0 0 0 1 1 0 1 0.73125 1 0 0 0 1 1 1 0 0.72500 1 0 0 0 1 1 1 1 0.71875 1 0 0 1 0 0 0 0 0.71250 1 0 0 1 0 0 0 1 0.70625 1 0 0 1 0 0 1 0 0.70000 1 0 0 1 0 0 1 1 0.69375 1 0 0 1 0 1 0 0 0.68750 1 0 0 1 0 1 0 1 0.68125 1 0 0 1 0 1 1 0 0.67500 1 0 0 1 0 1 1 1 0.66875 1 0 0 1 1 0 0 0 0.66250 table 2-2. voltage identification definition (sheet 4 of 5) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v cc_max
datasheet volume 1 of 2 19 electrical specifications notes: 1. when the ?11111111? vid pattern is observed, or when the sktocc# pin is deasserted, the voltage regulator output should be disabled. 2. shading denotes the expected vid range of th e intel xeon processor e7-8800/4800/2800 product families processor. 3. the vid range includes vid transitions that may be initiated by thermal events, extended halt state transitions, higher c-states or enhanced intel? speedstep technology transitions. the extended halt state must be enabled for the processor to remain within its specifications 4. once the vrm/evrd is operating after power-up, if ei ther the output enable signal is de-asserted or a specific vid off code is received, the vrm/evrd must turn off its output (the output should go to high impedance) within 500 ms and latch o ff until power is cycled. refer to voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 11.1 design guidelines. 2.3 signal groups the signals are grouped by buffer type an d similar characteristics, as listed in ta b l e 2 - 3 . the buffer type indicates which signaling technology and specifications apply to the signals. all the differential signals have on die termination (odt) resistors. there are some signals that do not have odt and need to be terminated on the board. the signals which have odt are listed in ta b l e 2 - 4 . 1 0 0 1 1 0 0 1 0.65625 1 0 0 1 1 0 1 0 0.65000 1 0 0 1 1 0 1 1 0.64375 1 0 0 1 1 1 0 0 0.63750 1 0 0 1 1 1 0 1 0.63125 1 0 0 1 1 1 1 0 0.62500 1 0 0 1 1 1 1 1 0.61875 1 0 1 0 0 0 0 0 0.61250 1 0 1 0 0 0 0 1 0.60625 1 0 1 0 0 0 1 0 0.60000 101000 1 10. 59375 101001 0 00. 58750 101001 0 10. 58125 101001 1 00. 57500 101001 1 10. 56875 101010 0 00. 56250 101010 0 10. 55625 101010 1 00. 55000 101010 1 10. 54375 101011 0 00. 53750 101011 0 10. 53125 101011 1 00. 52500 101011 1 10. 51875 101100 0 00. 51250 101100 0 10. 50625 101100 1 00. 50000 111111 1 0 off 111111 1 1 off table 2-2. voltage identificati on definition (sheet 5 of 5) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v cc_max
electrical specifications 20 datasheet volume 1 of 2 table 2-3. signal groups (sheet 1 of 2) signal group type signals 1 system reference clock differential differential pair, hstl sy sclk_dp, sysclk_dn, sysclk_lai_n, sysclk_lai intel? qpi interface signal groups differential scid 2 input qpi[3:0]_drx_d[n/p][19:0], qpi[3:0]_clkrx_d[p/n] differential scid 2 output qp i[3:0]_dtx_d[n/p][19:0], qpi[3:0]_clktx_d[p/n] intel? smi signals differential inputs fbd0nbiclk[a/b][p/n]0 fbd1nbiclk[c/d][p/n]0 differential output fbd0sboclk[a/b][p/n]0 fbd1sboclk[c/d][p/n]0 differential input fbd0nbi[a/b][p/n][13:0] fbd1nbi[c/d][p/n][13:0] differential output fbd0sbo[a/b ][p/n][10:0], fbd1sbo[c/d][p/ n][10:0] tap single ended gtl tck, tdi,tms, trst_n single ended gtl-open drain tdo peci single ended cmos peci smbus single ended cmos smbclk, smbdat, sm_wp spd bus single ended cmos i/od spdclk, spddat strap pins single ended gtl bootmode[1:0] single ended cmos sktid[2:0] flash rom port single ended gtl - od flashrom_cfg[2:0], flashrom_dati flashrom_cs[3:0]_n, flashrom_clk, flashrom_dato, flashrom_wp_n error bus single ended gtl input, gtl open drain output error[0]_n, error[1]_n power up, resets single ended cmos input pwrgood, viopwrgood, single ended gtl input runbist, reset_n thermal single ended gtl input force_pr_n single ended gtl mem_throttle[1]_n,mem_throttle[0]_n single ended gtl-open drain prochot_n, thermtrip_n single ended cmos - open drain thermalert_n
datasheet volume 1 of 2 21 electrical specifications 2.4 processor dc specifications voltage and current specifications are detailed in ta b l e 2 - 5 . for platform planning refer to ta b l e 2 - 6 , which provides vcc static and transient tolerances. differential sysclk specifications are found in ta b l e 2 - 2 6 . control sideband and test access port (tap) are listed in ta b l e 2 - 2 4 . ta b l e 2 - 5 through ta b l e 2 - 2 4 list the dc specifications for the processor and are valid only while meeting specifications for case temperature (t case as specified in chapter 6, ?thermal specifications? ), clock frequency, and input volt ages. care should be taken to read all notes associated with each parameter. vid single ended cmos output vid[7:0], cvid[7:1] single ended open/ground vio_vid[4:1] voltage, and voltage regulator differential power isense_dn, isense_dp single ended power vcc, vreg, vcache, vcachesense, vcc33,vcoresense, vio, psi_cache_n,psi_n, vsscachesense,vsscoresense, debug single ended gtl i/o-od mbp[7:0]_n, prdy_n,preq_n notes: 1. see chapter 5 for signal descriptions. table 2-4. signals with r tt signals with rtt ? qpi[3:0]r[p/n]dat[19:0], qpi[5:4]r[p/n]clk0, qpi[3:0]t[p/n]dat[19:0], qpi[5:4]t[p/n]clk0 ? fbd0nbiclk[a/b][p/n]0, fbd1nbiclk[c/d][p/n]0, fbd0sboclk[a/b][p/n]0, fbd1sboclk[c/d][p/n]0, fbd0nbi[a/b][p/n][12:0], fbd1nbi[c/d][p/ n][12:0], fbd0sbo[a/b][p/n][9:0], fbd1sbo[c/d][p/n][9:0]. table 2-3. signal groups (sheet 2 of 2) signal group type signals 1 table 2-5. voltage and current specifications (sheet 1 of 2) symbol parameter voltage plane min typ max unit notes 1 vid vcore vid range n/a 0.60 1.35 v 4,5 vcc v cc for processor core launch - fmb see ta b l e 2 - 6 v 4,5,6 vcc ll vcc load line 0.8 m cvid vcache vid range 0.7 1.35 v 4,5 v cache vcc for cache see ta b l e 2 - 7 v4,5,7 v cache ll v cache load line 1.4 m v vid_step vcc vid step size during a transition n/a 6.25 mv
electrical specifications 22 datasheet volume 1 of 2 notes: 1. dc for a power supply is define d as any variation less than 1 mhz. 2. 1% tolerance 3. 1% ripple, 2% total as measur ed at vr remote sense point 4. unless otherwise noted, all specifications in this table apply to all processors . these specifications are based on pre-silicon characterization and will be updated as further data becomes available. 5. individual processor vid values may be calibrated du ring manufacturing such that two devices at the same speed may have different settings. 6. the v cc voltage specification requirements are measured across vias on the platform for the vcoresense and vsscoresense pins close to the socket with a 100 mhz bandwidth osc illoscope, 1.5 pf maximum v vid_shift total allowable dc load line shift from vid steps n/a lltype +/ -15mv mv vio_vid processor i/o supply voltage 1.053 1.0875 1.1 1,3 v reg pll supply voltage (dc + ac specification) n/a 1.8 v 1,2 vcc33 package component voltage 3.135 3.3 3.465 v icc_max vcc33 iccmax for vcc33 75 ma i cc_max i cc for intel xeon processor e7-8800/4800/2800 product families processor 130w tdp with multiple vid launch - fmb vcc vcache v io v reg 120 75 18.1 1.5 a i cc for intel xeon processor e7-8800/4800/2800 product families processor 105w tdp with multiple vid launch - fmb vcc vcache v io v reg 115 70 17.6 1.5 a i cc for intel xeon processor e7-8800/4800/2800 product families processor 95w tdp with multiple vid launch - fmb vcc vcache v io v reg 115 70 17.6 1.5 a i cc_tdc thermal design current (tdc) intel xeon processor e7- 8800/4800/2800 product families processor 130w tdp launch - fmb vcc vcache v io v reg 110 55 16.0 1.3 a thermal design current (tdc) intel xeon processor e7- 8800/4800/2800 product families processor 105w tdp launch - fmb vcc vcache v io v reg 90 50 16.0 1.3 a thermal design current (tdc) intel xeon processor e7- 8800/4800/2800 product families processor 95w tdp launch - fmb vcc vcache v io v reg 85 50 15.5 1.3 a psi tdc thermal design current launch - fmb 130w 105w 95w 22 25 21 a psi_cache tdc thermal design current launch - fmb 130w 105w 95w 45 45 45 a table 2-5. voltage and current specifications (sheet 2 of 2) symbol parameter voltage plane min typ max unit notes 1
datasheet volume 1 of 2 23 electrical specifications probe capacitance, and 1 m minimum impedance. the maximum leng th of ground wire on the probe should be less than 5 mm. ensure external noise fr om the system is not coupled in the scope probe. 7. the v cache voltage specification requirements are measured across vias on the platform for the vcachesense and vsscachesense pins close to the so cket with a 100 mhz ba ndwidth oscilloscope, 1.5 pf maximum probe capacitance, and 1 m minimum impedance. the maximum length of ground wire on the probe should be less than 5 mm. ensure external noise from the system is not coupled in the scope probe. notes: 1. the vcc _min and vcc _max loadlines represent static an d transient limits. please see ta b l e 2 - 8 and figure 2-3 for vcc overshoot specifications. 2. the loadlines specify voltage limits at the die. di e vcc voltage is available at the vcoresense and vsscoresense lands and should be measured there. voltage regulation feedba ck for voltage regulator circuits must be taken from the processor vcores ense and vsscoresense lands. voltage regulation feedback for voltage regulator circuits must al so be taken from processor vcccoresense and vsscoresense lands. refer to the voltage regulator module (vrm) an d enterprise voltage regulator down (evrd) 11.1 design guidelines for socket load line guidelines and vr implementation table 2-6. processor vcc stat ic and transient tolerance i cc (a) vcc _max (v) vcc _typ (v) vcc _min (v) notes 0 vid - 0.000 vid - 0.015 vid - 0.030 - 5 vid - 0.004 vid - 0.019 vid - 0.034 10 vid - 0.008 vid - 0.023 vid - 0.038 15 vid - 0.012 vid - 0.027 vid - 0.042 20 vid - 0.016 vid - 0.031 vid - 0.046 25 vid - 0.020 vid - 0.035 vid - 0.050 30 vid - 0.024 vid - 0.039 vid - 0.054 35 vid - 0.028 vid - 0.043 vid - 0.058 40 vid - 0.032 vid - 0.047 vid - 0.062 45 vid - 0.036 vid - 0.051 vid - 0.066 50 vid - 0.040 vid - 0.055 vid - 0.070 55 vid - 0.044 vid - 0.059 vid - 0.074 60 vid - 0.048 vid - 0.063 vid - 0.078 65 vid - 0.052 vid - 0.067 vid - 0.082 70 vid - 0.056 vid - 0.071 vid - 0.086 75 vid - 0.060 vid - 0.075 vid - 0.090 80 vid - 0.064 vid - 0.079 vid - 0.094 85 vid - 0.068 vid - 0.083 vid - 0.098 90 vid - 0.072 vid - 0.087 vid - 0.102 95 vid - 0.076 vid - 0.091 vid - 0.106 100 vid - 0.080 vid - 0.095 vid - 0.110 105 vid - 0.084 vid - 0.099 vid - 0.114 110 vid - 0.088 vid - 0.103 vid - 0.118 115 vid - 0.092 vid - 0.107 vid - 0.122 120 vid - 0.096 vid - 0.111 vid - 0.126 125 vid - 0.100 vid - 0.115 vid - 0.130 130 vid - 0.104 vid - 0.119 vid - 0.134 135 vid - 0.108 vid - 0.123 vid - 0.138 140 vid - 0.112 vid - 0.127 vid - 0.142 145 vid - 0.116 vid - 0.131 vid - 0.146 150 vid - 0.120 vid - 0.135 vid - 0.150
electrical specifications 24 datasheet volume 1 of 2 notes: 1. the vcc _min and vcc _max loadlines represent static an d transient limits. please see ta b l e 2 - 8 and figure 2-3 for vcc overshoot specifications. figure 2-1. vcc static and transient tolerance table 2-7. processor vcccache st atic and transient tolerance i cc (a) vcc _max (v) vcc _typ (v) vcc _min (v) notes 0 vid - 0.000 vid - 0.015 vid - 0.030 5 vid - 0.007 vid - 0.022 vid - 0.037 10 vid - 0.014 vid - 0.029 vid - 0.044 15 vid - 0.021 vid - 0.036 vid - 0.051 20 vid - 0.028 vid - 0.043 vid - 0.058 25 vid - 0.035 vid - 0.050 vid - 0.065 30 vid - 0.042 vid - 0.057 vid - 0.072 35 vid - 0.049 vid - 0.064 vid - 0.079 40 vid - 0.056 vid - 0.071 vid - 0.086 45 vid - 0.063 vid - 0.078 vid - 0.093 50 vid - 0.070 vid - 0.085 vid - 0.100 55 vid - 0.077 vid - 0.092 vid - 0.107 60 vid - 0.084 vid - 0.099 vid - 0.114 65 vid - 0.091 vid - 0.106 vid - 0.121 70 vid - 0.098 vid - 0.113 vid - 0.128 75 vid - 0.105 vid - 0.120 vid - 0.135 80 vid - 0.112 vid - 0.127 vid - 0.142 0.8 mohm load line -0.15 -0.14 -0.13 -0.12 -0.11 -0.10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.00 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 load (a) vcc normalized droop (v) vcc max vcc min vcc typ
datasheet volume 1 of 2 25 electrical specifications 2. the loadlines specify voltage limits at the die. die vcccache voltage is available at the vcachesense and vsscachesense lands and should be measured there. voltage regulation feedback for voltage regulator circuits must also be taken from the processor vcachesense and vsscachesense lands. refer to the voltage regulator module (vrm) an d enterprise voltage regulator down (evrd) 11.1 design guidelines for socket load line guidelines and vr implementation. the intel xeon processor e7-8800/4800/2800 product families processor can tolerate short transient overshoot events where supp lied voltage exceeds the vid/cvid voltage when transitioning from a high-to-low current load condition. this overshoot cannot exceed vid/cvid + v os_max . (v os_max is the maximum allowable overshoot above vid/cvid). these specifications apply to the processor die voltages, as measured with respect to vsscoresense, and vsscachesense. figure 2-2. vcache static and transient tolerance table 2-8. v cc and vcache overshoot specification symbol parameter min max units figure notes v os_max magnitude of vcc overshoot above vid 0.05 v 2-3 t os_max time duration of v cc overshoot above vid 25 s 2-3 1.4 mohm load line -0.15 -0.14 -0.13 -0.12 -0.11 -0.10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.00 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 load (a) vcc normalized droop (v) vcc max vcc min vcc typ
electrical specifications 26 datasheet volume 1 of 2 2.5 intel ? qpi and intel ? scalable memory interconnect (intel ? smi) interface differential signaling the intel xeon processor e7-8800/4800/2800 product families processor intel qpi and intel ? scalable memory interconnect (intel ? smi) signals use differential links. the termination voltage level for the intel xeon processor e7-8800/4800/2800 product families processor for uni-directional serial differential links, each link consisting of a pair of opposite-polarity (d+, d-) signals is v ss . termination resistors are provided on the processor silicon and are terminated to v ss . intel chipsets also provide on-die terminat ion (odt), thus eliminating the need to terminate the links on the system board for the intel qpi and intel smi signals. figure 2-4 illustrates the active odt. signal listings are included in ta b l e 2 - 3 and ta b l e 2 - 4 . see chapter 5 for the pin signal definitions. all of the signals on the processor intel qpi and intel smi signals are in the differential signal group. figure 2-3. overshoot example waveform 0 5 10 15 20 25 time [us] voltage [v] vid - 0.000 vid + 0.050 v os t os t os : overshoot time above vid v os : overshoot voltage above vid figure 2-4. active odt for a differential link example t x r x r tt r tt r tt r tt signal signal
datasheet volume 1 of 2 27 electrical specifications 2.5.1 intel qpi signaling specifications intel qpi electrical specifications call out specifications that are common across all platforms and specifications that target in tel qpi within enterprise mp class server systems. 2.5.1.1 intel qpi referenc e clocking specifications reference clock requirements required by the pll as measured at the package pin. ta b l e 2 - 9 provides a list of system clock specifications. figure 2-5. validation topology for testin g specifications of the reference clock figure 2-6. differential waveform measurement points table 2-9. system clock sp ecifications (sheet 1 of 2) symbol parameter min nom max unit notes f refclk system clock frequency 133.33 mhz er refclk-diffrise, er refclk-difffall rise and fall slope parameter 1.0 4.0 v/nsec v refclk-max single ended maximum voltage with overshoot 1150 mv v refclk-min single ended minimum voltage with overshoot -350 mv v cross absolute crossing point limits between refclk+ and refclk- waveforms 250 550 mv see figure 2-6 v cross_delta peak-peak variation in crossing points 140 see figure 2-6 v refclk_diff-ih high of the differential voltage (v refclk + - v refclk -) above zero 150 mv
electrical specifications 28 datasheet volume 1 of 2 note: 1. the given pll parameters are: underdamping (z ) = 0.8 and natural frequency = fn = 7.86e6 hz; w n = 2 * fn. n_minui = 12 for intel qpi phy 1 channel. 2.5.1.2 link speed inde pendent specifications link speed independent specifications call ou t the transmitter and receiver parameters required at all link speeds. the transmitter sp ecifications are for stand-alone, individual transmitters (tx). the validation setup for tx is called out in figure 2-7 . the parameters for the receiver (rx) couple the transmitter with the worst-case interconnect. the validation setup for rx is called out in figure 2-8 . v refclk_diff-il low of the differential voltage (v refclk + - v refclk -) above zero -150 mv t refclk-dutycycle duty cycle of reference clock. 40 50 60 % t refclk-jitter-rms-onepll accumulated rms jitter over n ui of a given pll model output in response to the jittery reference clock input. the pll output is generated by convolving the measured reference clock phase jitter with a given pll transfer function. here n=12. 0.5 psec 1 trefclk-diff-jit phase drift between clocks at two connected ports 500 psec trefclk-c2c-jit short term difference in the period of any two adjacent clock cycles 100 psec at via table 2-9. system clock specifications (sheet 2 of 2) symbol parameter min nom max unit notes figure 2-7. setup for validating standa lone tx voltage and timing parameters tx package silicon tx ideal loads si tx pin terminations are set to optimum values (targeted around 50 ohms single-ended)
datasheet volume 1 of 2 29 electrical specifications specifications for link speed independent specifications are called out in ta b l e 2 - 1 0 . figure 2-8. setup for validating tx + wo rst-case interconnect specifications s ilic o n t x bit (data) w orst-c a se intercon nect ide a l loads tx package s ilic o n t x b it (c lock) id ea l loads lossless interconnect phase m a tche d to d a ta b it interco nne ct table 2-10. link speed independent specifications (sheet 1 of 2) symbol parameter min nom max unit notes uiavg average ui size at ?g? gt/ s (where g = 4.8, 6.4, and so on) 0.999 * nominal 1000/g 1.001 * nominal psec t rise-fall-pin-20-80 +/- 100mv@crossing 25 psec 0.25 ui z tx_low_cm_dc defined as: (max(z tx_low_cm_dc ) - min(z tx_low_cm_dc )) / z tx_low_cm_dc expressed in %, over full range of tx single ended voltage -6 6 % of z tx_low_cm_dc z rx_low_cm_dc defined as: (max(z tx_low_cm_dc ) - min(z tx_low_cm_dc )) / z tx_low_cm_dc expressed in %, over full range of tx single ended voltage -6 0 6 % of z tx_low_cm_dc rl rx return loss of receiver package measured at any data or clock signal inputs see note 1 n min-ui-validation # of ui over which the eye mask voltage and timing spec needs to be validated 1,000,000 z rx_high_cm_dc single ended dc impedance to gnd for either d+ or d- of any data bit at tx 40k 2 z tx_link_detect link detection resistor 500 2000 v tx_link_detect link detection resistor pull-up voltage 1.5 v v diff_idle voltage difference between d+ and d- when lanes are either in electrical idle or v tx_link_detect 0.1 * v rx- diff-pp-pin v
electrical specifications 30 datasheet volume 1 of 2 notes: 1. return loss specifications for receiver package are not provided. however, main taining a well impedance matched and low loss receiver package is crucial for a successful silic on operation, includ ing maintaining as low as possible on-die capacitance. 2. used during initialization. it is the state of ?off? condition for the receiver when only the minimum termination is connected 2.5.2 intel qpi electrical specifications the applicability of this section applies to intel qpi within a links-based enterprise mp class server platform. this section contains information for slow boot up speed (1/4 frequency of the reference clock), 4.8 gt/s, and 6.4 gt/s. the transfer rates available for the intel xeon processor e7-8800/4800/2800 product families processor are shown in ta b l e 2 - 1 1 . t data_term_skew skew between first to last data termination meeting z rx_low_cm_dc 128 ui t inband_reset_ sense time taken by inband reset detector to sense inband reset 1.5 s tc l k _det time taken by clock detector to observe clock stability 20k ui t clk_freq_det time taken by clock frequency detector to decide slow vs. operational clock after stable clock 32 reference clock cycles t refclk-tx-variability phase variability between reference clk (at tx input) and tx output. 500 psec t refclk-rx-variability phase variability between reference clk (at rx input) and rx output. 1000 psec l d+/d-rx-skew phase skew between d+ and d- lines for any data bit at rx 0.03 ui ber lane bit error rate per lane valid for 4.8 and 6.4 gt/s 1.0e-14 events voh_bscan output high during boundary scan vio-100 vio mv vol_bscan outpu t low during boundary scan 0100mv vih_bcan input high during boundary scan 0.86 * vio v vil_bscan outpu t low during boundary scan 0.40 * vio v table 2-10. link speed independen t specifications (sheet 2 of 2) symbol parameter min nom max unit notes table 2-11. clock frequency table intel qpi system interface forwarded clock frequency intel qpi system interface data transfer rate 33.33 mhz 66.66 mt/s 1 2.40 ghz 4.8 gt/s 3.20 ghz 6.4 gt/s
datasheet volume 1 of 2 31 electrical specifications 2.5.2.1 requirements at 1/4 refclk signaling rate the signaling rate is defined as 1/4 the rate of the system reference clock. for example, a 133 mhz system reference clock would have a forwarded clock frequency of 33.33 mhz and the signaling rate would be 66.66 mt/s. notes: 1. this speed is the 1/4 refclk frequency. table 2-12. parameter values for intel? qpi phy1 chan nel at 1/4 refclk frequency symbol parameter min nom max unit notes v tx-diff-pp-pin transmitter differential swing 800 1500 mv 1 z tx_low_cm_dc dc resistance of tx terminations at half the single ended swing (which is usually 0.25*v tx-diff-pp- pin ) bias point 37 47 z rx_low_cm_dc dc resistance of rx terminations at half the single ended swing (which is usually 0.25*v tx-diff-pp- pin ) bias point 37 47 v tx-cm-dc-pin transmitter output dc common mode, defined as average of v d+ and v d- 0.23 0.27 fraction of v tx-diff-pp-pin 5 v tx-cm-ac-pin transmitter output ac common mode, defined as ((v d+ + v d- )/2 - v tx-cm-dc-pin ) - 0.0375 0.0375 fraction of v tx-diff-pp-pin 2 tx duty-pin average of absolute ui-ui jitter -0.002 0.0025 ui 1 tx jitui-ui-1e-7-pin absolute value of ui-ui jitter measured at tx output pins with 1e-7 probability. -0.007 0.0075 ui 3 v rx-diff-pp-pin voltage eye opening at the end of tx+ channel for any data or clock channel measured with a cumulative probability of 1e-9 (ui). 150 v tx-diff-pp-pin mv t rx-diff-pp-pin timing eye opening at the end of tx+ channel for any data or clock channel measured with a cumulative probability of 1e-9 (ui). 0.9 1 ui t rx-data-clk-skew-pin delay of any data lane relative to the clock lane, as measured at the end of tx+ channel. this parameter is a collective sum of effects of data clock mismatches in tx and on the medium connecting tx and rx. 0.48 0.52 ui vrx-clk forward clk rx input voltage sensitivity (differential pp) 150 mv v rx-cm-dc-pin dc common mode ranges at the rx input for any data or clock channel 75 400 mv v rx-cm-ac-pin ac common mode ranges at the rx input for any data or clock channel, defined as: ((v d+ + v d- /2 - v rx-cm-dc-pin ) -50 50 mv 2
electrical specifications 32 datasheet volume 1 of 2 notes: 1. the ui size is dependent upon the reference clock frequency 2. 1300mvpp swing is recommended when cpu to cpu length is within 2? of pdg max trace length. note that default value is 1100mvpp. 3. measure ac cm noise at the tx and decimate to its spectral components. for all spectral components above 3.2ghz, apply the attenuation of the channel at the ap propriate frequency. if the resultant ac cm at the receiver is met after taking out the appropriate spectr al component and it meets the rx ac cm spec then we can allow the transmitter ac cm noise to pass. 4. dc cm can be relaxed to 0.20 min and 0.30 max vdi ffp-p swing if rx has wide dc common mode range. 2.5.2.2 requirements for 4.8 gt/s and 6.4 gt/s electrical specifications for tx and rx for 4.8 gt/s are captured in ta b l e 2 - 1 3 and for 6.4 gt/s are captured in ta b l e 2 - 1 4 . table 2-13. parameter values for intel qpi channel at 4.8 gt/s (sheet 1 of 2) symbol parameter min nom max unit notes v tx-diff-pp-pin transmitter differential swing 800 1500 mv 1 z tx_low_cm_dc dc resistance of tx terminations at half the sing le ended swing (which is usually 0.25*v tx-diff-pp- pin ) bias point 37 47 z rx_low_cm_dc dc resistance of rx terminations at half the sing le ended swing (which is usually 0.25*v tx-diff-pp- pin ) bias point 37 47 v tx-cm-dc-pin transmitter output dc common mode, defined as average of v d+ and v d- 0.23 0.27 fraction of v tx-diff-pp- pin v tx-cm-ac-pin transmitter output ac common mode, defined as ((v d+ + v d- )/2 - v tx-cm-dc-pin ) - 0.0375 0.0375 fraction of v tx-diff-pp- pin 2 tx duty-pin average of ui-ui jitter. -0.025 0.03 ui tx jitui-ui-1e-7-pin ui-ui jitter measured at tx output pins with 1e-7 probability. -0.065 0.07 ui 3 tx jitui-ui-1e-9-pin ui-ui jitter measured at tx output pins with 1e-9 probability. -0.07 0.076 ui tx clk-acc-jit-n_ui-1e-7 p-p accumulated jitter out of transmitter over 0 <= n <= n ui where n=12, measured with 1e-7 probability. 00.15ui tx clk-acc-jit-n_ui-1e-9 p-p accumulated jitter out of transmitter over 0 <= n <= n ui where n=12, measured with 1e-9 probability. 00.17ui t tx-data-clk-skew-pin delay of any data lane relative to clock lane, as measured at tx output -0.5 0.5 ui v rx-diff-pp-pin voltage eye opening at the end of tx+ channel for any data or clock channel measured with a cumulative probability of 1e-9 (ui). 225 1200 mv t rx-diff-pp-pin timing eye opening at the end of tx+ channel for any data or clock channel measured with a cumulative probability of 1e-9 (ui) 0.63 1 ui
datasheet volume 1 of 2 33 electrical specifications notes: 1. 1300mvpp swing is recommended when cpu to cpu length is within 2? of pdg max trace length. note that default value is 1100mvpp. 2. measure ac cm noise at the tx and decimate to its spectral components. for all spectral components above 3.2ghz, apply the attenuation of the channel at the ap propriate frequency. if the resultant ac cm at the receiver is met after taking out the appropriate spectral components meets the rx ac cm spec then we can allow the transmitter ac cm noise to pass. 3. measured with victim lane running clock pattern, neighboring aggressor lanes running dc pattern and far aggressor lanes running prbs pattern. t rx-data-clk-skew-pin delay of any data lane relative to the clock lane, as measured at the end of tx+ channel. this parameter is a collective sum of effects of data clock mismatches in tx and on the medium connecting tx and rx. -1 3 ui vrx-clk forward clk rx input voltage sensitivity (differential pp) 180 mv v rx-cm-dc-pin dc common mode ranges at the rx input for any data or clock channel 125 350 mv v rx-cm-ac-pin ac common mode ranges at the rx input for any data or clock channel, defined as: ((v d+ + v d- /2 - v rx-cm-dc-pin ) -50 50 mv 2 table 2-13. parameter values for intel qpi channel at 4.8 gt/s (sheet 2 of 2) symbol parameter min nom max unit notes table 2-14. parameter values for intel qpi at 6.4 gt/s (sheet 1 of 2) symbol parameter min nom max unit notes v tx-diff-pp-pin transmitter differential swing 800 1500 mv 1 z tx_low_cm_dc dc resistance of tx terminations at half the single ended swing (which is usually 0.25*v tx-diff-pp- pin ) bias point 38 47 z rx_low_cm_dc dc resistance of rx terminations at half the single ended swing (which is usually 0.25*v tx-diff-pp- pin ) bias point 38 47 v tx-cm-dc-pin transmitter output dc common mode, defined as average of v d+ and v d- 0.23 0.27 fraction of v tx-diff-pp-pin 4 v tx-cm-ac-pin transmitter output ac common mode, defined as ((v d+ + v d- )/2 - v tx-cm-dc-pin ) -0.065 0.065 fraction of v tx-diff-pp-pin 2 tx duty-pin average of absolute ui-ui jitter - 0.0325 0.0325 ui tx jitui-ui-1e-7-pin ui-ui jitter measured at tx output pins with 1e-7 probability. -0.12 0.12 ui 3 tx jitui-ui-1e-9-pin ui-ui jitter measured at tx output pins with 1e-9 probability. -0.137 0.137 ui tx clk-acc-jit-n_ui-1e-7 p-p accumulated jitter out of transmitter over 0 <= n <= n ui where n=12, measured with 1e-7 probability. 00.2ui tx clk-acc-jit-n_ui-1e-9 p-p accumulated jitter out of transmitter over 0 <= n <= n ui where n=12, measured with 1e-9 probability. 00.23ui
electrical specifications 34 datasheet volume 1 of 2 notes: 1. 1300 mvpp swing is recommended when cpu to cpu length is within 2? of pdg max trace length. note that default value is 1100mvpp. 2. measure ac cm noise at the tx and decimate to its spectral components. for all spectral components above 3.2 ghz, apply the attenuation of the channel at the ap propriate frequency. if the resultant ac cm at the receiver is met after taking out th e appropriate spectral components meets the rx ac cm spec then we can allow the transmitter ac cm noise to pass. 3. measured with victim lane running clock pattern, neighboring aggressor lanes running dc pattern and far aggressor lanes running prbs pattern. 4. dc cm can be relaxed to 0.20 and 0.30 vdiffp-p swing if rx has wide dc common mode range. 2.5.3 intel smi signaling specifications this section defines the high-speed differential point-to-point signaling link for intel smi. the link consists of a transmitter and a receiver and the interconnect in between them. the specifications described in th is section covers 6.4 gb/s operation. reference intel smi high-speed differential ptp link is at 1.5 v. 2.5.4 intel smi transmitter and receiver specifications all tx-rx links are dc-coupled and the tx and rx pins adhere to the return loss specifications for continuous transmission operation. t tx-data-clk-skew-pin delay of any data lane relative to clock lane, as measured at tx output -0.5 0.5 ui v rx-diff-pp-pin voltage eye opening at the end of tx+ channel for any data or clock channel measured with a cumulative probability of 1e-9 (ui). 155 1200 mv 2 t rx-diff-pp-pin timing eye opening at the end of tx+ channel for any data or clock channel measured with a cumulative probability of 1e-9 (ui) 0.61 1 ui t rx-data-clk-skew-pin delay of any data lane relative to the clock lane, as measured at the end of tx+ channel. this parameter is a collective sum of effects of data clock mismatches in tx and on the medium connecting tx and rx. -1 3 ui vrx-clk forward clk rx input voltage sensitivity (differential pp) 150 mv v rx-cm-dc-pin dc common mode ranges at the rx input for any data or clock channel 90 350 mv v rx-cm-ac-pin ac common mode ranges at the rx input for any data or clock channel, defined as: ((v d+ + v d- /2 - v rx-cm-dc-pin ) -50 50 mv table 2-14. parameter values for intel qpi at 6.4 gt/s (sheet 2 of 2) symbol parameter min nom max unit notes
datasheet volume 1 of 2 35 electrical specifications table 2-15. parameter values for intel smi at 6.4 gt/s and lower (sheet 1 of 2) symbol parameter min nom max unit notes v tx-diff-pp-pin transmitter differential swing 800 1200 mv z tx_low_cm_dc dc resistance of tx terminations at half the single ended swing (which is usually 0.25*v tx-diff-pp- pin ) bias point 37 47 z rx_low_cm_dc dc resistance of rx terminations at half the single ended swing (which is usually 0.25*v tx-diff-pp- pin ) bias point 37 47 vtx-diff-pp-clk-pin transmitter differential swing using a clk like pattern 0.9*mi n(vtx- diff-pp pin) max(vtxdi ff-pp-pin) mv 1 v tx-cm-dc-pin transmitter output dc common mode, defined as average of v d+ and v d- 0.20 0.30 fraction of v tx-diff-pp-pin 3 v tx-cm-ac-pin transmitter output ac common mode, defined as ((v d+ + v d- )/2 - v tx-cm-dc-pin ) -0.20 0.20 fraction of v tx-diff-pp-pin tx duty-ui-pin this is computed as absolute difference between average value of all ui with that of average of odd ui, which in magnitude would equal absolute difference between average of all ui and average of all even ui. - 0.0325 0.0325 ui tx1ui-rj-noxtalk-pin rj value of 1-ui jitter, using setup of figure 2-7 . with x-talk off, but on-die system like noise present. this extraction is to be done after software correction of dcd 00.008ui2 tx1ui-dj-noxtalk--pin pp dj value of 1-ui jitter with x- talk off, but on-die system like noise present. -0.01 0.01 ui 2 txn-ui-rj-noxtalkpin rj value of n-ui jitter. with x-talk off, but on-die system like noise present. here 1 < n < 9.this extraction is to be done after software correction of dcd 00.012ui2 txn-ui-dj-noxtalkpin pp dj value of n-ui jitter. with x- talk off, but on-die system like noise present. here 1 < n < 9.dj here indicated djdd of dual-dirac fitting, after software correction of dcd -0.04 0.04 0.2 ui 2 t tx-data-clk-skew-pin delay of any data lane relative to clock lane, as measured at tx output -0.5 0.5 ui t rx-data-clk-skew-pin delay of any data lane relative to the clock lane, as measured at the end of tx+ channel. this parameter is a collective sum of effects of data clock mismatches in tx and on the medium connecting tx and rx. -1 3.5 ui vrx-clk forward clk rx input voltage sensitivity (differential pp) 150 mv vrx-vmargin any data lane rx input voltage (differential pp) measured at ber=1e-9 100 mv
electrical specifications 36 datasheet volume 1 of 2 notes: 1. this is the swing specification for th e forwarded clk output. note that this specification will also have to be suitably de-embedded for package/pcb loss to translate the value to the pad, since there is a significant variation between traces in a setup. 2. while the x-talk is off, on-die no ise similar to that occurring with a ll the transmitter and receiver lanes toggling will still need to be presen t. when a socket is not present in the transmitter measurement setup, in many cases the contribution of the cross-talk is not significant or can be estimated within tolerable error even with all the transmitter lanes sending patterns. therefore for all tx measurements, use of a socket should be avoided. the contribution of cross-talk may be significant and should be done using the same setup at tx and compared against the expectations of full link signaling. note that there may be cases when one of dj and rj specs is met and another violat ed in which case the signaling analysis should be run to determine link feasibility. 3. dc cm can be relaxed to 0.20 and 0.30 vdiffp-p swing if rx has wide dc common mode range. 2.5.4.1 summary of transmitter amplitude specifications trx-tmargin timing width for any data lane using repetitive patterns (check validation conditions) and clean forwarded clk, measured at ber=1e-9 0.8 ui trx-tmargin-dcd-clk magnitude of degradation of timing width for any data lane using repetitive patterns with dcd injection in forwarded clk measured at ber=1e-9, compared to trx-tmargin. the magnitude of dcd is specified under validation conditions. 0.02 ui trx-tmargin-rj-clk magnitude of degradation of timing width for any data lane using repetitive patterns with only rj injection in forwarded clk measured at ber=1e-9, compared to trx-tmargin. the magnitude of rj is specified under validation conditions. 0.11 ui trx-tmargin-dcd-rj- clk magnitude of degradation of timing width for any data lane using repetitive patterns with dcd and rj injection in forwarded clk measured at ber=1e-9, compared to trx-tmargin. the magnitude of dcd and rj is specified under validation conditions. 0.12 ui v rx-cm-dc-pin dc common mode ranges at the rx input for any data or clock channel, defined as average of vd+ and vd-. 125 350 mv v rx-cm-ac-pin ac common mode ranges at the rx input for any data or clock channel, defined as: ((v d+ + v d- /2 - v rx-cm-dc-pin ) -50 50 mv table 2-15. parameter values for intel smi at 6.4 gt/s and lower (sheet 2 of 2) symbol parameter min nom max unit notes table 2-16. pll specification for tx and rx symbol parameter min max units notes f pll-bw_tx-rx -3db bandwidth 4 16 mhz jitpk tx-rx jitter peaking 3 db
datasheet volume 1 of 2 37 electrical specifications table 2-17. transmitter voltage swing voltage swing setting mean v tx-diffp-p-min mean v tx-diffp-p-max units 110 (l) 850 1200 mv 100 (m) 700 1000 mv 010 (s) 600 850 mv table 2-18. transmitter de-emphasis (swing setting 110: large) de-emphasis range measured values after inverse equalization de-emphasis setting v tx-de-ratio- min v tx-de-ratio- max minimum swing maximum swing units normalized swing delta (max) 10.1 db 9.3 11.0 680 1315 mv 0.450 8.5 db 7.8 9.3 685 1305 mv 0.400 7.2 db 6.6 7.8 700 1300 mv 0.390 6.0 db 5.5 6.6 700 1285 mv 0.300 5.0 db 4.5 5.5 700 1285 mv 0.290 table 2-19. transmitter de-emphasi s (swing setting 100: medium) de-emphasis range measured values after inverse equalization de-emphasis setting v tx-de-ratio- min v tx-de-ratio- max minimum swing maximum swing units normalized swing delta (max) 8.5 db 7.8 9.3 555 1100 mv 0.420 7.2 db 6.6 7.8 570 1095 mv 0.410 6.0 db 5.5 6.6 570 1095 mv 0.320 5.0 db 4.5 5.5 570 1095 mv 0.315 4.1 db 3.7 4.5 570 1090 mv 0.295 3.3 db 2.9 3.7 570 1090 mv 0.270 table 2-20. transmitter de-empha sis (swing setting 010: small) de-emphasis range measured values after inverse equalization de-emphasis setting v tx-de-ratio- min v tx-de-ratio- max minimum swing maximum swing units normalized swing delta (max) 6.0 db 5.5 6.6 485 930 mv 0.345 5.0 db 4.5 5.5 485 930 mv 0.335 4.1 db 3.7 4.5 485 930 mv 0.320 3.3 db 2.9 3.7 485 930 mv 0.295 2.5 db 2.1 2.9 485 930 mv 0.290 1.8 db 1.5 2.1 485 930 mv 0.285
electrical specifications 38 datasheet volume 1 of 2 2.5.4.2 summary of transmi tter output specifications notes: 1. specified at the package pins into a ti ming and voltage compliance test load. 2. the maximum value is specified to be at least (v tx-diffp-p l / 4) + v tx-cm l + (v tx-cm-acp-p / 2) 3. measured from the reference clock edge to the center of the output eye. this sp ecification must be met across specified voltage and temperature ranges fo r a single component. drift rate of change is significantly below the tracking capability of the receiver. 2.5.4.3 intel? smi differential receiver input specifications the receiver definition starts from the input pin of the receiver end package and therefore includes the package and the receiver end device. 2.5.4.3.1 receiver input compliance eye specification following the specification of the transmitter, the receiver is specified in terms of the minimum input eye height that must be maintained at the input to the receiver, and under which the receiver must function at th e specified data rates. in addition to eye height, there are timing specifications that must also be met for both the data lanes and the forwarded clock. the receiver eye is referenced to v ss and all input terminations at the receiver must be referenced to v ss . this input eye must be maintained for the entire duration of the rx test pattern. an appropriate average transmitter ui must be used as the interval for table 2-21. summary of differential transmitter output specifications symbol parameter min max units comments v tx-cm-ratio ratio of v tx-cm to measured v tx-diffp-p (dc) 23 27 % v tx-cm-ac-ratio ratio of v tx-cm-acp-p to measured v tx-diffp-p (dc) 7.5 % v tx-se single-ended voltage (w.r.t. vss) on d+/d- -75 750 mv 1, 2 t tx_tj transmitter total jitter 0.25 t tx_dj transmitter dual-dirac deterministic jitter 0.15 ui t tx_pws transmitter pulse width shrinkage (data) 0.05 t tx_clk_pws transmitter pulse width shrinkage (forwarded clock) 0.018 ui er tx-rise , er tx-fall differential tx output edge rates 10 30 v/ns differential voltage levels at 100 mv measured as: note 1 rl tx-diff differential return loss 8 db measured relative to 50 ohms over 0.1 ghz to 3.2 ghz. rl tx-cm common mode return loss 6 db measured relative to 50 ohms over 0.1 ghz to 3.2 ghz. r tx transmitter termination resistance 37.4 47.6 l tx-skew lane-to-lane skew at tx 100 + 2 ui ps l tx-skew-clk-dat tx clock-to-data skew -0.2 0.2 ns forwarded clock delay - data delay l tot-skew-clk-dat total system clock-to-data skew -1.5 1.5 ns t tx-drift maximum tx drift 240 ps 3 ber bit error ratio 10 -12
datasheet volume 1 of 2 39 electrical specifications measuring the eye diagram. the eye diagram is created using all edges of the rx test pattern. the eye diagrams shall be measured by observing a continuous pattern at the pin of the device. note that the persistent eye diagram is used for determining conformance to voltage level specifications only. 2.5.4.4 receiver input timing the figure of merit for receiver input timing is the rx eye width, represented by the symbol t rx-eye-min . the receiver eye width is measured with respect to a delayed version of the transmitted forwarded clock, as described in section 2.5.4.5 . 2.5.4.5 summary of receiver input specifications figure 2-9. required receiver input eye (differential) sh owing minimum voltage specs v rx-difp-p-min v rx-diff = 0mv (d+ d- crossing point) v rx-diff = 0mv (d+ d- crossing point) table 2-22. summary of differential rece iver input specifications (sheet 1 of 2) symbol parameter min max units comments v rx-diffp-p differential peak-to-peak input voltage 115 1200 mv v rx-diffp-p = 2*|v rx-d+ - v rx-d- | measured as: note 1 ; see also note 2 v rx-se single-ended voltage (w.r.t. vss) on d+/d- -200 750 mv 3 v rx-diff-pulse single-pulse peak differential input voltage 85 mv 3, 4 v rx-diff-adj-ratio amplitude ratio between adjacent symbols, v rx-diffp-p <= 1100 mv 4.0 3, 5 t rx-eye-min minimum rx eye width 0.50 ui 3, 6, 7 t rx-dj-dd max rx eye closure due to dual- dirac deterministic jitter 0.40 ui 3, 6, 8, 9 t rx-pw-zc single-pulse width at zero-voltage crossing 0.55 ui 3, 4 t rx-pw-ml single-pulse width at minimum- level crossing 0.2 ui 3, 4 v rx-cm-mineh common mode of the input voltage (v rx-diffp-p = v rx-diffp-p-min ) 120 310 mv v rx-cm = dc (avg) of |v rx-d+ + v rx-d- |/2 v rx-cm-eh-ratio ratio of v rx-diffp-p increase to max dc common mode increase (v rx- diffp-p > v rx-diffp-p-min ) 1v rx-diffp-p >= v rx-diffp-p-min + v rx-cm-eh-ratio * (v rx-cm - 310 mv)
electrical specifications 40 datasheet volume 1 of 2 notes: 1. specified at the package pins into a timing and voltage compliant test setup. 2. the v rx-diffp-p pin specification reflects a target eye height at the pad equal to 70 mv. 3. specified at the package pins into a ti ming and voltage compliance test setup. 4. the single-pulse mask provides sufficient symbol energy for reliable rx reception. each symbol must comply with both the single-pulse mask and the cumulative eye mask. 5. the relative amplitude ratio limit between adjacent symbols pr events excessive inter-symbol interference in the rx. each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols. 6. this number does not include the effects of ssc or reference clock jitter. 7. the t rx-eye-min pin specification reflects a target eye width at the pad equal to 0.45 ui. 8. the t rx-dj-dd pin specification reflects a target max dete rministic jitter at the pad equal to 0.45 ui. 9. defined as the dual-dirac determin istic jitter at the receiver input. 10. allows for 15 mv dc offset between transmit and receive devices. 11. the received differential signal must satisfy both this ratio as well as the absolute maximum ac peak-to-peak common mode specification. for example, if v rx-diffp-p is 200 mv, the maximum ac peak-to-peak common mode is the lesser of (200 mv * 0.45 = 90 mv) and v rx-cm-acp-p . 12. one of the components that contribute to the deterioration of the return loss is the esd structure which needs to be careful ly designed. 13. the termination small signal resistance; tolerance over the entire signaling voltage range shall not exceed 5 . 14. measured from the reference clock edge to the center of the input eye. this specification mu st be met across specified volta ge and temperature ranges for a single compone nt. drift rate of change is significan tly below the tracking capability of the receiver. 2.6 platform environmental control interface (peci) dc specifications peci is an intel proprietary interface that provides a communication channel between intel processors and chipset components to external thermal monitoring devices. the intel xeon processor e7-8800/4800/2800 product families processor contains a digital thermal sensor (dts) that reports a relative die temperature as an offset from t cc v rx-cm-abs common mode of the input voltage (absolute max) 375 mv v rx-cm = dc (avg) of |v rx-d+ + v rx-d- |/2 v rx-cm-acp-p ac peak-to-peak common mode of input voltage 270 mv v rx-cm-ac = max |v rx-d+ + v rx-d- |/2? min |v rx-d+ + v rx-d- |/2 measured as: note 1 v rx-cm-ac-eh-ratio ratio of v rx-cm-acp-p to minimum v rx-diffp-p 45 % 11 rl rx-diff differential return loss 9 db measu red over 0.1ghz to 3.2 ghz. see also note 12 rl rx-cm common mode return loss 6 db measu red over 0.1ghz to 3.2 ghz. see also note 12 r rx rx termination resistance 37.4 47.6 ohm t rx-skew-clk-data rx skew between clock and data 0.0 1.0 ns forwarded clock delay - data delay t rx-drift minimum rx drift tolerance 600 ps 14 t fr-entry -detect fast reset entry detect time 240 ui ber bit error ratio 10 -12 table 2-22. summary of differential rece iver input specifications (sheet 2 of 2) symbol parameter min max units comments
datasheet volume 1 of 2 41 electrical specifications activation temperature. temperature se nsors located throughout the die are implemented as analog-to-digital converters ca librated at the factory. peci provides an interface for external devices to read pr ocessor die and dram temperatures, perform processor manageability functions, and ma nage processor interface tuning and diagnostics. 2.6.1 dc characteristics the peci interface operates at a nominal voltage set by v ioc . the set of dc electrical specifications shown in ta b l e 2 - 2 3 is used with devices normally operating from a v ioc interface supply. v ioc nominal levels will vary between processor families. all peci devices will operate at the v ioc level determined by the processor installed in the system. for specific nominal v ioc levels, refer to ta b l e 2 - 2 3 . note: 1. v ioc supplies the peci interface. peci behavior does not affect v ioc min/max specifications. 2. it is expected that the peci driver will take in to account, the variance in the receiver input thresholds and consequently, be able to drive its out put within safe limits (-0.15v to 0.275*v ioc for the low level and 0.725*v ioc to v ioc +0.15 for the high level). 3. the leakage specification applies to powered devices on the peci bus. 4. one node is counted for each client and one node for the system host. extended trace lengths might appear as additional nodes. 5. excessive capacitive loading on the peci line may slow down the signal rise/fall times and consequently limit the maximum bit rate at which the interface can operate. 2.6.2 input device hysteresis the input buffers in both client and host models must use a schmitt-triggered input design for improved noise immunity. use figure 2-10 as a guide for input buffer design. table 2-23. peci dc electrical limits symbol definition and conditions min max units notes 1 v in input voltage range -0.150 v ioc + 0.15 v v hysteresis hysteresis 0.1 * v ioc v v n negative-edge threshold voltage 0.275 * v ioc 0.50 * v ioc v2 v p positive-edge threshold voltage 0.55 * v ioc 0.725 * v ioc v2 i sink low level output sink (v ol = 0.25 * v ioc ) 0.5 1.0 ma i leak+ high impedance state leakage to v ioc (v leak = v ol ) n/a 50 a 3 i leak- high impedance leakage to gnd (v leak = v oh ) n/a 25 a 3 c bus bus capacitance per node n/a 10 pf 4,5 v noise signal noise immunity above 300 mhz 0.1 * v ioc n/a v p-p
electrical specifications 42 datasheet volume 1 of 2 2.7 dc specifications notes: 1. unless otherwise noted, all specifications in this table apply to a ll processor frequencies. 2. the v io referred to in these specifications refers to instantaneous v io. 3. based on a test load of 50 to v ioc. 4. specified for synchronous signals. 5. r sys_term is the termination on the system, not part of the processor. 6. intel ? trusted execution technology for servers input leakage current maximum is 50 ua. figure 2-10. input device hysteresis table 2-24. tap, strap pins, error, poweru p, reset, thermal, vid signal group dc specifications symbol parameter min typ max units notes 1 v il input low voltage -0.1 0.54 * v iof v2,3 v ih input high voltage 0.86 * v iof v2 v ol output low voltage v ioc * r on / (r on + r sys_term ) v 2,5 v oh output high voltage v ioc v2 rtt on die pull up termination 42.5 50 57.5 ohm t co t co time from sysclk pin till signal valid at output 0.5 2.9 ns 3 setup time control sideband input signals with respect to sysclk 900 ps 4 hold time control sideband input signals with respect to sysclk 900 ps 4 poc/ reset setup time power-on configuration setup time 2sysclk poc/ reset hold time power-on configuration hold time 108 sysclk r on control sideband buffer on resistance 818ohm i li input leakage current 200 a6 minimum v p maximum v p minimum v n maximum v n peci high range peci low range valid input signal range minimum hysteresis v io peci ground
datasheet volume 1 of 2 43 electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. recommended strapping high is 1k - 10k . 3. recommended strapping low is <100 . 2.8 ac specifications the processor timings specified in this section are defined at the processor pads. therefore, proper simulation of the signals is the only means to verify proper timing and signal quality. ta b l e 2 - 2 6 through ta b l e 2 - 2 8 list the ac specifications associated with the processor. see chapter 5 for signal definitions. the timings specified in this section should be used in conjunction with the processor signal integrity models provided by intel. in tel qpi, smi and sideband layout guidelines are also available in the appropriate platform design guidelines. note: care should be taken to read all notes associated with a particular timing parameter. table 2-25. miscellaneo us dc specifications pin parameter min typ max units notes 1 sktid[2:0] input low voltage <0.54 v ioc v3 input high voltage >0.7 v cc v2 leakage limit low 5 ua 3 leakage limit high 4.2 ma 2 thermalert leakage limit low 2.6 ma 3 leakage limit high 5 ua table 2-26. system reference clock ac specifications (sheet 1 of 2) symbol parameter min nom max unit figure notes f refclk (ssc-off) system reference clock frequency 133.29 133.33 133.37 mhz f refclk (ssc-on) system reference clock frequency 132.62 133.33 133.37 mhz t rise, t fall rise time, fall time. 175 700 ps 1, 2 t refclk-dutycycle duty cycle of reference clock. 40 50 60 % period 3 er refclk-diff-rise , er refclk-diff-fall differential rising and falling edge rates 14v/ns 3, 4 c i- ck clock input capacitance 0.2 1.0 pf vl differential input low voltage -0.15 v 3 vh differential input high voltage 0.15 v 3 v cross absolute crossing point 0.25 0.35 0.55 v 1, 5, 6 v cross (rel) relative crossing point 0.25 + 0.5*(vh avg - 0.700) 0.55 + 0.5*(vh avg - 0.700) 5, 7 v cross delta v cross variation - - 0.14 v 1, 5, 8 v max (absolute overshoot) single-ended maximum voltage - - 1.15 v 1, 9
electrical specifications 44 datasheet volume 1 of 2 notes: 1. measurement taken from single ended waveform. 2. rise and fall times are measured single ende d between 245 mv and 455 mv of the clock swing. 3. measurement taken from differential waveform. 4. measured from -150 mv to +150 mv on the differential wave form (derived from refclk+ minus reflclk). the signal must be monotic through the measurement region for rise and fa ll time. the 300 mv measurement window is centred on the differential zero crossing. see figure 2-25 5. measured at crossing point where the instantaneous voltage value of the rising edge refclk+ equals the falling edge refclk-. see figure 2-26 . 6. refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. see figure 2-26 . 7. vhavg is the statistical average of the vh measured by the oscilloscope. the purpose of defining relative crossing point voltages is to prevent a 250 mv vcross with a 850 mv vh. also this prevents the case of a 550 mv vcross with a 660 mv vh. see figure 2-21 . 8. defined as the total variation of all cr ossing voltages of rising refclk+ and falling refclk-. th is is the maximum allowed variance in vcross for any particular system. see figure 2-27. 9. defined as the maximum instantaneous voltage including overshoot. see figure 2-26. 10. defined as the minimum instantaneous voltage including overshoot. see figure 2-26. 11. tstable is the time the differential clock must maintain a minimum 150 mv differential voltage after rising/falling edges before it is allowed to droop back into the vrb 100 mv range. see figure 2-22 . v min (absolute undershoot) single-ended minimum voltage -0.3 - - v 1, 10 vrb-diff differential ringback voltage threshold -100 100 mv 3, 11 t stable allowed time before ringback 500 ps 3, 11 table 2-27. miscellaneous gtl ac specifications t# parameter min max unit figure notes 1, 2 asynchronous gtl input pulse width 8 sysclks error[0]_n, error[1]_n, thermtrip_n, prochot_n output edge rate 0.7 2.3 v/ns 1, 3 error[0]_n pulse width 16 16 b-clocks mem_throttle0_n, mem_throttle1_n, intel txt, runbist, input edge rate 0.5 v/ns force_pr_n pulse width 500 s 2-18 prochot_n pulse width 500 s 2-18 pwrgood rise time 20 ns pwrgood, reset_n, force_pr_n, error[0]_n, error[1]_n, sktdis_n input edge rates 0.1 v/ns 2, 3, 4 reset_n hold time w.r.t sysclk/sysclk_n 0.5 ns 2-11 5 reset_n pulse width while pwrgood is active 1 ms sysclk stable to pwrgood assertion 10 sysclk thermtrip_n assertion until vcc, and vcccache removal 500 ms 2-12 vcc stable to pwrgood assertion 0.05 500 ms v reg stable to pwrgood assertion 1 ms v io stable to viopwrgood assertion 1 500 ms viopwrgood de-assertion to v io outside specification 100 ns viopwrgood rise time 20 ns pwrgood assertion to reset_n de-assertion 34 ms table 2-26. system reference clock ac specifications (sheet 2 of 2) symbol parameter min nom max unit figure notes
datasheet volume 1 of 2 45 electrical specifications notes: 1. these values are based on driving a 50 transmission line into a 50 pullup. 2. deterministic reset. 3. inspection range is vil max to vih min. when a signal ledge presents between vil and vih region, measure the first edge rate from vil (or vih) to the first inflection point, then measure the second edge rate from the second inflection poin t to vih (or vil) and divide the sum of the two edge rates by two, to generate the final edge rate number. 4. error signals are 0.1 v/ns if non-monotonic, and 0.05 v/ns if monotonic. 5. for production platforms, reset determinism is not required. notes: 1. see voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 11.1 design guidelines for addition information. 2. platform support for vid transitions is required for the processor to operat e within specifications. table 2-28. vid signal group ac specifications t # parameter min max unit figure notes 1, 2 vid step time --s 2-29 vid down transition to valid v ccp (min) --s 2-28 , 2-29 vid up transition to valid v ccp (min) --s 2-28 , 2-29 vid down transition to valid v ccp (max) --s 2-28 , 2-29 vid up transition to valid v ccp (max) --s 2-28 , 2-29 figure 2-11. reset_n setup/hold time for deterministic reset_n deassertion figure 2-12. thermtrip_n power down sequence thold tsetup reset_n sysclk_n sysclk v il v ih note: deterministic reset_n is defined for reset _n deassertion only (c oming out of reset_n) t a = thermtrip_n assertion until v cc and v cache removal thermtrip_n v cc, v cache t a
electrical specifications 46 datasheet volume 1 of 2 notes: 1. these parameters are based on design characterization and are not tested. 2. all ac timings for the smbus signals are referenced at v il_max or v il_min and measured at the processor pins. refer to figure 2-14 . 3. rise time is measured from (v il_max - 0.15v) to (v ih_min + 0.15v). fall time is measured from (0.9 * vcc33) to (v il_max - 0.15v). 4. minimum time allowed between request cycles. 5. following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next transaction. figure 2-13. vid step times table 2-29. smbus and spdbus signal group ac timing specifications symbol parameter min max unit figure notes 1, 2 transmitter and receiver timings f smb smbclk frequency 10 100 khz tck smbclk period 10 100 s t low smbclk high time 4 s 2-14 t high smbclk low time 4.7 s 2-14 t r smbus rise time 1 s 2-14 3 t f smbus fall time 0.3 s 2-14 3 t aa smbus output valid delay 0.1 4.5 s 2-15 t su;dat smbus input setup time 250 ns 2-14 t hd;dat smbus input hold time 0 ns 2-14 vil, smbus smbus vil -0.3 vcc33 x 0.3 v vih, smbus smbus vih vcc33 x 0.7 vcc33 + 0.5 v vol, smbus smbus vol vcc >2.5 0.4 v smbus vol vcc <= 2.5 0.2 v t buf bus free time between stop and start condition 4.7 s 2-14 4, 5 t hd;sta hold time after repeated start condition 4.0 s 2-14 t su;sta repeated start condition setup time 4.7 s 2-14 t su;std stop condition setup time 4.0 s 2-14 vid n n-1 m+1 m ... ta tb tc td ta = vid down to valid v cc (max) tb = vid down to valid v cc (min) tc = vid up to valid v cc (max) td = vid up to valid v cc (min) v cc (max) v cc (min)
datasheet volume 1 of 2 47 electrical specifications notes: 1. all input edge rates are specified between v il (max) and v ih (min), and output edge rates are specified between v ol (max) and v oh (min). 2. these values are based on driving a 50 transmission line into a 50 pullup. figure 2-14. smbus timing waveform figure 2-15. smbus valid delay timing waveform table 2-30. flashrom signal gr oup ac timing specifications symbol parameter min max unit figure notes f flashrom flashrom_clk frequency 0 66.67 mhz slew datai flashrom_dati edge rate 0.5 v/ns 1 slew datao flashrom_dato edge rate 0.7 2.3 v/ns 2 t cs_as flashrom_cs[3:0]_n assertion before first flashrom_clk 10 ns 2-16 t cs_de flashrom_cs[3:0]_n deassertion after last flashrom_clk 12 ns 2-16 t setup flashrom_dati setup time 6 ns 2-16 t hold flashrom_dati hold time 0 ns 2-16 t delay flashrom_dato valid delay ?2.0 2.0 ns 2-16 data clk p p s s stop stop start start t low t r t hd;sta t hd;dat t buf high t t su;dat t t su;sta t hd;sta su;sto t f data output data valid sm_clk sm_dat taa
electrical specifications 48 datasheet volume 1 of 2 notes: 1. not 100% tested. these parameters are based on design characterization. 2. it is recommended that tms be assert ed while trst_n is being deasserted. 3. this specification is based on the capabilities of the itp-xdp debug port tool, not on processor silicon. 4. referenced to the rising edge of tck. 5. specification for a minimum swing defined between tap v t- to v t+ . this assumes a minimum edge rate of 0.5 v/ns. 6. referenced to the falling edge of tck. 7. trst_n must be held asserted for 2 tck periods to be guaranteed that it is recognized by the processor. figure 2-16. flashrom timing waveform table 2-31.tap signal group ac timing specifications symbol parameter min max unit figure notes 1, 2 transmitter and receiver timings f tap tck frequency 66 mhz 2-17 3 t p tck period 15 ns t s tdi, tms setup time 7.5 ns 2-17 4, 5 t h tdi, tms hold time 7.5 ns 2-17 4, 6 t x tdo clock to output delay 7.5 24 ns 2-17 6 trst_n assert time 30 ns 2-18 7 t delay t setup t hold t cs_de t cs_as flashrom_cs flashrom_clk flashrom_dato flashrom_dati figure 2-17. tap valid delay timing waveform tx = tdo clock to output delay ts = tdi, tms setup time th = tdi, tms hold time v=0.5*vio tck signal tx ts th v valid v tp tp = tap frequency
datasheet volume 1 of 2 49 electrical specifications 2.9 processor ac timing waveforms the following figures are used in conj unction with the ac timing tables, ta b l e 2 - 2 6 through ta b l e 2 - 2 8 . note: for figure 2-21 through figure 2-29 , the following apply: ? all common clock ac timings signals are referenced to the crossing voltage (v cross ) of the sysclk_dp, sysclk_dn at rising edge of sysclk_dp. ? all source synchronous ac timings are re ferenced to their associated strobe (address or data). source synchronous data signals are referenced to the falling edge of their associated data strobe. source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. ? all ac timings for the tap signals are referenced to the tck at 0.5 * v io at the processor lands. all tap signal timings (tms , tdi, and so on) are referenced at 0.5 * v io at the processor die (pads). ? all cmos signal timings are referenced at 0.5 * v io at the processor lands. the intel qpi electrical test setup are shown in figures figure 2-19 and figure 2-20 . figure 2-18. test reset (trst_n), force_pr_n, reset_n and prochot_n pulse width waveform v t q t q = pulse width v = 0.5*vccio figure 2-19. intel qpi system interfac e electrical test setup for validating standalone tx voltage and timing parameters tx package silicon tx ideal loads si tx pin terminations are set to optimum values (targeted around 42.5 ohms single-ended)
electrical specifications 50 datasheet volume 1 of 2 figure 2-20. intel qpi system interfac e electrical test setup for validating tx + worst-case interc onnect specifications figure 2-21. differe ntial clock waveform s ilic o n t x bit (d ata) w orst-c ase in tercon n ect id ea l loads tx package s ilic o n t x bit (c lock) ideal loads lossless interconnect phase m atch e d to d ata b it interco nn ect crossing voltage threshold region vh vl overshoot undershoot ringback margin rising edge ringback falling edge ringback, bclk0 bclk1 crossing voltage tp tp = t1: bclk[1:0] period
datasheet volume 1 of 2 51 electrical specifications figure 2-22. differential cl ock crosspoint specification figure 2-23. system common cloc k valid delay timing waveform figure 2-24. differential measurement point for ringback 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 200 250 300 350 400 450 500 550 600 650 vhavg (mv) crossing point (mv) 550 mv 250 mv 250 + 0.5 (vhavg - 700) 550 + 0.5 (vhavg - 700) bclk0 bclk1 common clock signal (@ driver) common clock signal (@ receiver) t0 t1 t2 t q t r valid valid valid t p t p = t10: common clock output valid delay t q = t11: common clock input setup t r = t12: common clock input hold time
electrical specifications 52 datasheet volume 1 of 2 figure 2-25. differential measuremen t points for rise and fall time figure 2-26. single-ended measurement po ints for absolute cross point and swing figure 2-27. single-ended measurem ent points for delta cross point
datasheet volume 1 of 2 53 electrical specifications figure 2-28. voltage sequence timing requirements vccio vccreg vcache vcore bclk/bclk_n pwrgood reset_n 10 bclks min 34ms min vio_pwrgood cvids vids ~25ms max* cvid (vcccache set and does not change after reset) boot voltage=1.1v vid (fused values) pcu will determine initial vid value after reset is deasserted vccreg_good =vcache_outen vcache_vr_rdy =vcore_outen vcore_vr_rdy 200 ring osc clocks, max ~ 4us for 50mhz vid poc sktdis_n reset straps 108 bclks min. 0.05ms-3ms* vcore adjusts accordingly. vids start driving at vcache=0.75v microseconds 0.05ms-3.5ms* boot voltage=1.1v 0.05ms-3ms* 0.05ms-3.5ms* vio related pins must not be driven above vccio. resistive pull-ups need to be tied to vccio; actively driven signals must be gated by viopwrgood vid poc latched 0ms-5ms* vccio to powergood: no max bootmode[1:0], lt-sx, flashrom_cfg[2:0], sktdis # , runbist 3.3v 1 sktocc_n 2 5 100ms min 7 4 9 6 10 sktid[2:0] 8 2bclks setup vr11.0 dg rev 2.0) vccio_outen
electrical specifications 54 datasheet volume 1 of 2 note: 1. 3.3 v supplies power to on-package parts, including the pirom/oem scratch pad. 3.3v must be up at a minimum of 100ms before pwrgood is asserted. 2. sktocc_n is pulled to an appropriate platform rail; when socket is occupied, package pulls the signal to vss. here, sktocc_n is assumed pulled to 3.3 v. 3. viovids are pulled up to an appropriate platform rail. the package pulls appropriate vio vids to vss. 4. for integrated memory, millbrook is sequenced afte r vio is true. system implementation decides whether installed hot plug memory cards are sequenced with or after system power is up. 5. smb, sm_wp, spd, sktid inputs/bidir are 3.3 v-rai l related pins. all other misc io are vio-related, including other strapping pins (bootmode pins), int and error (bidir). vio related pins must not be driven above vccio. resistive pull-ups need to be tied to vccio; actively driven signals must be gated by viopwrgood. 6. weak pullups/downs assumed on vid pins, for vid poc sampling. 7. reset_n is an asynchronous input for normal production usage. 8. sktid must be valid with 3.3v for proper pirom/oem scratch pad addressing and must stay valid. sktid is latched by processor only on a pwrgood toggle. skti d must be driven valid before the assertion of pwrgood on a cold-reset. 9. reset straps: during all resets, reset-latched straps must meet the following se tup and hold. cold reset: must be stable 2 bclks prior to assertion of pwrgood and reset warm reset: must be stable 2 bclks prior to assertion of reset hold time: must be stable 108 bclks hold after deasserti on of reset. reset-latched straps include bootmode, intel ? trusted execution technology for servers, flashrom_cfg[2:0], sktdis_n, and runbist. bootmode & intel txt pins are latched only after a processor cold-reset (that is, system power-up or pwrgood-reset). runbist: is reset-deassertion latched. it is a dynamic signal. (system can assert, during runtime but mu st meet reset setup/hold requirements). 10. sktdis_n has no affect on inputs. it also has no impact to smb pins and package-strapped pins (sktocc_n, procid_n). the following outputs are not tri-stated by sktdis#: tdo, psi_n, psi_cache_n, vids, and cvids. sktdis _n is transparent while reset is asserted. sktdis_n is latched at reset assertion. note: sktdis_n has no impact on inte rnal logic (logic is not disabled). a pwrgood-reset might be required when the skt is "enabled" again. 11. * indicates a vr11.1 value. 12. suggested normal power down should have the opposite sequence. at the minimum, intel xeon processor e7-8800/4800/2800 product families processor vrs can be disabled in parallel subject to the power rail?s capacitive drain time. 13. in order to ensure timestamp counter (tsc) synchronization across sockets in multi-socket systems, the reset# de-assertion edge should arrive at the same bclk rising edge on all sockets and should meet tsu (setup) and th (hold) requirements. this is relative to the first cold reset in the system. the delay from cold to any warm reset needs to be the same on each socket. figure 2-29. vid step times and vcc waveforms
datasheet volume 1 of 2 55 electrical specifications 2.10 flexible motherboard guidelines the flexible motherboard (fmb) guidelines are estimates of the maximum ratings that the intel xeon processor e7-8800/4800/2800 product families processor will have over certain time periods. the ratings are only es timates as actual specifications for future processors may differ. the vr 11.1 specification is developed to meet fmb voltage specification values required by all inte l xeon processor e7-8800/4800/2800 product families processor skus. 2.11 reserved (rsvd) or unused signals all reserved signals must be left unconnected on the motherboard. any deviation in connection of these signals to any power rail or other signals can result in component malfunction or incompatibility with future processors. see chapter 4 for socket land listing of the processor and the location of all signals, including rsvd signals. unused intel qpi or intel smi input ports may be left as no-connects. 2.12 test access port connection the recommended tap connectivity will be de tailed in an upcoming document release. 2.13 mixing processors intel supports and validates multiple proc essor configurations only in which all processors operate with the same intel qpi frequency, core frequency, power segment, have the same number of cores, and have the same internal cache sizes. mixing components operating at different internal clock frequencies is not supported and will not be validated by intel. combining processo rs from different power segments is also not supported. 2.14 processor spd interface the processor spd interface is used for memo ry initialization including the set up and use of the memory thermal sensor on-board the intel ? 7500 scalable memory buffer. base board management controllers (bmc) can use the peci interface to the spd engine for access to this thermal data. the spd master in the processor supports 100 khz operation and the following set of commands: send byte and receive byte write byte and read byte write word and read word the spd interface does not support bus arbitration or clock stretching.
electrical specifications 56 datasheet volume 1 of 2
datasheet volume 1 of 2 57 processor package mechanical specifications 3 processor package mechanical specifications 3.1 package mechanical specifications the processor is packaged in a flip-chip land grid array (fc-lga8) package that interfaces with the motherboard via an lga1567 socket. the package consists of a processor mounted on a substrate land-carrier. an integrated heat spreader (ihs) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. figure 3-1 shows a sketch of the processor package components and how they are assembled together. note: processor package mechanical information an d drawings provided in this section are preliminary and subject to change. the package components shown in figure 3-1 include the following: 1. integrated heat spreader (ihs) 2. processor core (die) 3. package substrate 4. capacitors note: 1. socket and motherboard are included for reference and are not part of processor package. figure 3-1. processor pa ckage assembly sketch socket system board capacitors ihs substrate ihs substrate die socket system board capacitors ihs substrate ihs substrate die
processor package mechanical specifications 58 datasheet volume 1 of 2 3.1.1 package mechanical drawing the package mechanical drawings are shown in figure 3-2 and figure 3-3 . the drawings include dimensions necessary to design a thermal solution for the processor. all drawing dimensions are in mm. these dimensions include: 1. package reference with tolerances (total height, length, width, etc.) 2. ihs parallelism and tilt 3. land dimensions 4. top-side and back-side component keep-out dimensions 5. reference datums
datasheet volume 1 of 2 59 processor package mechanical specifications figure 3-2. processor package drawing (sheet 1 of 2)
processor package mechanical specifications 60 datasheet volume 1 of 2 figure 3-3. processor packag e drawing (sheet 2 of 2)
datasheet volume 1 of 2 61 processor package mechanical specifications 3.1.2 processor compon ent keep-out zones the processor may contain components on the substrate that define component keep-out zone requirements. a thermal and mechanical solution design must not intrude into the required keep-out zones. decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. see figure 3-2 and figure 3-3 for keep-out zones. the location and quantity of package capacitors may change due to manufacturing efficiencies bu t will remain within the component keep-in. 3.1.3 package loading specifications ta b l e 3 - 1 provides dynamic and static load spec ifications for the processor package. these mechanical maximum load limits shou ld not be exceeded during heatsink assembly, shipping conditions, or standard use condition. also, any mechanical system or component testing should not exceed the maximum limits. the processor package substrate should not be used as a mechanic al reference or load -bearing surface for thermal and mechanical solution. the mi nimum loading specification must be maintained by any thermal and mechanical solutions. . notes: 1. these specifications apply to uniform compressive loading in a dire ction normal to the processor ihs. 2. this is the maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface. 3. these specifications are based on limited testing fo r design characterization. loading limits are for the package only and do not include th e limits of the processor socket. 4. dynamic loading is defined as an 11-ms duration average load su perimposed on the static load requirement. 3.1.4 package handling guidelines ta b l e 3 - 2 includes a list of guidelines on pa ckage handling in terms of recommended maximum loading on the processor ihs relati ve to a fixed substrate. these package handling loads may be experien ced during heatsink removal. 3.1.5 package insert ion specifications the processor can be inserted into and removed from an lga1567 socket 15 times. table 3-1. processor lo ading specifications parameter maximum notes static compressive load 755 n allowable load on the package ihs see notes 1, 2, 3 dynamic compressive load 490 n see notes 1, 3, 4 transient bend load 778 n see note 4 table 3-2. package handling guidelines parameter maximum notes shear 355 n tensile 155 n torque 7.9 n-m
processor package mechanical specifications 62 datasheet volume 1 of 2 3.1.6 processor mass specification the typical mass of the processor is ~40g . this mass [weight] includes all the components that are included in the package. 3.1.7 processor materials ta b l e 3 - 3 lists some of the package components and associated materials. 3.1.8 processor markings figure 3-4 shows the topside markings on the proc essor. this diagram is to aid in the identification of the processor. table 3-3. processor materials component material integrated heat spreader (ihs) nickel plated copper substrate fiber reinforced resin substrate lands gold plated copper figure 3-4. processor top-side markings table 3-4. mark content mark id value notes line 1 intel [m] [c] ?yy line 2 sub-brand sspec - sub brand line 3 sspec xxxxx s-spec: product specification number xxxxx: country of origin line 4 proc# freq/cache/intc intc: processor interconnect speed line 5 {fpo} {e4} {final proc ess order number} {lead free} 2d matrix proc# s-spec fpo sn line 1 line 2 line 3 line 4 line 5 apo serial number
datasheet volume 1 of 2 63 processor package mechanical specifications 3.1.9 processor land coordinates figure 3-5 shows the top view of the processor land coordinates. the coordinates are referred to throughout the docume nt to identify processor lands. . figure 3-5. processor land coor dinates and quadrants, top view a 1 46 bm
processor package mechanical specifications 64 datasheet volume 1 of 2
datasheet volume 1 of 2 65 pin listing 4 pin listing 4.1 processor package bottom land assignments this section provides a sorted package bottom pin list in ta b l e 4 - 1 and ta b l e 4 - 2 . ta b l e 4 - 1 is a listing of all processor package bottom side lands ordered alphabetically by socket name, and ta b l e 4 - 2 is a listing ordered by land number. 4.1.1 processor pin list, sorted by socket name table 4-1. pin list, sorted by socket name (sheet 1 of 39) socket (emts) land # format io bootmode[0] bh10 gtl i bootmode[1] bh11 gtl i cvid[1] bl16 cmos o cvid[2] bk16 cmos o cvid[3] bj16 cmos o cvid[4] bm17 cmos o cvid[5] bl17 cmos o cvid[6] bm18 cmos o cvid[7] bl18 cmos o error0_n g3 gtl od io error1_n g4 gtl od io fbd0nbian[0] be8 differential i fbd0nbian[1] bf8 differential i fbd0nbian[10] bc6 differential i fbd0nbian[11] bc8 differential i fbd0nbian[12] bh6 differential i fbd0nbian[13] bk8 differential i fbd0nbian[2] bh8 differential i fbd0nbian[3] bl10 differential i fbd0nbian[4] bm8 differential i fbd0nbian[5] bk9 differential i fbd0nbian[6] bg5 differential i fbd0nbian[7] bf6 differential i fbd0nbian[8] be6 differential i fbd0nbian[9] bd5 differential i fbd0nbiap[0] bd8 differential i fbd0nbiap[1] bf9 differential i fbd0nbiap[10] bd6 differential i fbd0nbiap[11] bc7 differential i fbd0nbiap[12] bh7 differential i fbd0nbiap[13] bl8 differential i fbd0nbiap[2] bg8 differential i fbd0nbiap[3] bm10 differential i fbd0nbiap[4] bm9 differential i fbd0nbiap[5] bk10 differential i fbd0nbiap[6] bh5 differential i fbd0nbiap[7] bg6 differential i fbd0nbiap[8] be7 differential i fbd0nbiap[9] be5 differential i fbd0nbibn[0] bg4 differential i fbd0nbibn[1] bk6 differential i fbd0nbibn[10] bc4 differential i fbd0nbibn[11] bc3 differential i fbd0nbibn[12] bh2 differential i fbd0nbibn[13] bk2 differential i fbd0nbibn[2] bl6 differential i fbd0nbibn[3] bm5 differential i fbd0nbibn[4] bk5 differential i fbd0nbibn[5] bj4 differential i fbd0nbibn[6] bg1 differential i fbd0nbibn[7] bf1 differential i fbd0nbibn[8] be3 differential i fbd0nbibn[9] bd2 differential i fbd0nbibp[0] bf4 differential i fbd0nbibp[1] bj6 differential i fbd0nbibp[10] bd4 differential i fbd0nbibp[11] bc2 differential i fbd0nbibp[12] bj2 differential i fbd0nbibp[13] bk3 differential i fbd0nbibp[2] bl7 differential i table 4-1. pin list, sorted by socket name (sheet 2 of 39) socket (emts) land # format io
pin listing 66 datasheet volume 1 of 2 fbd0nbibp[3] bm6 differential i fbd0nbibp[4] bl5 differential i fbd0nbibp[5] bk4 differential i fbd0nbibp[6] bh1 differential i fbd0nbibp[7] bf2 differential i fbd0nbibp[8] be4 differential i fbd0nbibp[9] be2 differential i fbd0nbiclkan0 bj8 differential i fbd0nbiclkap0 bj9 differential i fbd0nbiclkbn0 bh3 differential i fbd0nbiclkbp0 bh4 differential i fbd0sboan[0] ba5 differential o fbd0sboan[1] ay7 differential o fbd0sboan[10] aw8 differential o fbd0sboan[2] aw5 differential o fbd0sboan[3] av6 differential o fbd0sboan[4] au7 differential o fbd0sboan[5] at8 differential o fbd0sboan[6] ap7 differential o fbd0sboan[7] an6 differential o fbd0sboan[8] ap8 differential o fbd0sboan[9] ar6 differential o fbd0sboap[0] ba6 differential o fbd0sboap[1] ay8 differential o fbd0sboap[10] av8 differential o fbd0sboap[2] ay5 differential o fbd0sboap[3] aw6 differential o fbd0sboap[4] av7 differential o fbd0sboap[5] at7 differential o fbd0sboap[6] ap6 differential o fbd0sboap[7] an5 differential o fbd0sboap[8] ar8 differential o fbd0sboap[9] at6 differential o fbd0sbobn[0] aw4 differential o fbd0sbobn[1] ay3 differential o fbd0sbobn[10] am4 differential o fbd0sbobn[2] aw2 differential o fbd0sbobn[3] av1 differential o fbd0sbobn[4] av3 differential o fbd0sbobn[5] ar2 differential o fbd0sbobn[6] an2 differential o table 4-1. pin list, sorted by socket name (sheet 3 of 39) socket (emts) land # format io fbd0sbobn[7] am1 differential o fbd0sbobn[8] ap3 differential o fbd0sbobn[9] ar4 differential o fbd0sbobp[0] av4 differential o fbd0sbobp[1] ay4 differential o fbd0sbobp[10] an4 differential o fbd0sbobp[2] ay2 differential o fbd0sbobp[3] aw1 differential o fbd0sbobp[4] av2 differential o fbd0sbobp[5] ar1 differential o fbd0sbobp[6] ap2 differential o fbd0sbobp[7] an1 differential o fbd0sbobp[8] ar3 differential o fbd0sbobp[9] at4 differential o fbd0sboclkan0 au5 differential o fbd0sboclkap0 at5 differential o fbd0sboclkbn0 au3 differential o fbd0sboclkbp0 au4 differential o fbd1nbiclkcn0 ab5 differential i fbd1nbiclkcp0 ac5 differential i fbd1nbiclkdn0 ab2 differential i fbd1nbiclkdp0 ac2 differential i fbd1nbicn[0] ac8 differential i fbd1nbicn[1] ad8 differential i fbd1nbicn[10] v8 differential i fbd1nbicn[11] y8 differential i fbd1nbicn[12] aa6 differential i fbd1nbicn[13] ac6 differential i fbd1nbicn[2] ae8 differential i fbd1nbicn[3] af6 differential i fbd1nbicn[4] ae5 differential i fbd1nbicn[5] ad6 differential i fbd1nbicn[6] aa8 differential i fbd1nbicn[7] w5 differential i fbd1nbicn[8] y7 differential i fbd1nbicn[9] u6 differential i fbd1nbicp[0] ab8 differential i fbd1nbicp[1] ad9 differential i fbd1nbicp[10] v7 differential i fbd1nbicp[11] w8 differential i fbd1nbicp[12] ab6 differential i table 4-1. pin list, sorted by socket name (sheet 4 of 39) socket (emts) land # format io
datasheet volume 1 of 2 67 pin listing fbd1nbicp[13] ac7 differential i fbd1nbicp[2] af8 differential i fbd1nbicp[3] af7 differential i fbd1nbicp[4] af5 differential i fbd1nbicp[5] ae6 differential i fbd1nbicp[6] aa7 differential i fbd1nbicp[7] y5 differential i fbd1nbicp[8] y6 differential i fbd1nbicp[9] v6 differential i fbd1nbidn[0] ab4 differential i fbd1nbidn[1] ae4 differential i fbd1nbidn[10] u4 differential i fbd1nbidn[11] w4 differential i fbd1nbidn[12] aa1 differential i fbd1nbidn[13] ac3 differential i fbd1nbidn[2] ag2 differential i fbd1nbidn[3] af3 differential i fbd1nbidn[4] ae2 differential i fbd1nbidn[5] ad1 differential i fbd1nbidn[6] y3 differential i fbd1nbidn[7] w2 differential i fbd1nbidn[8] v1 differential i fbd1nbidn[9] v3 differential i fbd1nbidp[0] aa4 differential i fbd1nbidp[1] ad4 differential i fbd1nbidp[10] u3 differential i fbd1nbidp[11] v4 differential i fbd1nbidp[12] ab1 differential i fbd1nbidp[13] ad3 differential i fbd1nbidp[2] ag3 differential i fbd1nbidp[3] af4 differential i fbd1nbidp[4] af2 differential i fbd1nbidp[5] ad2 differential i fbd1nbidp[6] y4 differential i fbd1nbidp[7] y2 differential i fbd1nbidp[8] w1 differential i fbd1nbidp[9] v2 differential i fbd1sboclkcn0 k6 differential o fbd1sboclkcp0 j6 differential o fbd1sboclkdn0 k1 differential o fbd1sboclkdp0 j1 differential o table 4-1. pin list, sorted by socket name (sheet 5 of 39) socket (emts) land # format io fbd1sbocn[0] p5 differential o fbd1sbocn[1] n6 differential o fbd1sbocn[10] r8 differential o fbd1sbocn[2] m6 differential o fbd1sbocn[3] l5 differential o fbd1sbocn[4] l8 differential o fbd1sbocn[5] h7 differential o fbd1sbocn[6] j8 differential o fbd1sbocn[7] n8 differential o fbd1sbocn[8] r7 differential o fbd1sbocn[9] h5 differential o fbd1sbocp[0] r5 differential o fbd1sbocp[1] p6 differential o fbd1sbocp[10] p8 differential o fbd1sbocp[2] m7 differential o fbd1sbocp[3] m5 differential o fbd1sbocp[4] l7 differential o fbd1sbocp[5] h6 differential o fbd1sbocp[6] k8 differential o fbd1sbocp[7] n7 differential o fbd1sbocp[8] r6 differential o fbd1sbocp[9] j5 differential o fbd1sbodn[0] p2 differential o fbd1sbodn[1] n1 differential o fbd1sbodn[10] r4 differential o fbd1sbodn[2] n3 differential o fbd1sbodn[3] l1 differential o fbd1sbodn[4] k2 differential o fbd1sbodn[5] h2 differential o fbd1sbodn[6] j4 differential o fbd1sbodn[7] m4 differential o fbd1sbodn[8] p4 differential o fbd1sbodn[9] h3 differential o fbd1sbodp[0] r2 differential o fbd1sbodp[1] p1 differential o fbd1sbodp[10] r3 differential o fbd1sbodp[2] n2 differential o fbd1sbodp[3] l2 differential o fbd1sbodp[4] k3 differential o fbd1sbodp[5] h1 differential o fbd1sbodp[6] k4 differential o table 4-1. pin list, sorted by socket name (sheet 6 of 39) socket (emts) land # format io
pin listing 68 datasheet volume 1 of 2 fbd1sbodp[7] m3 differential o fbd1sbodp[8] n4 differential o fbd1sbodp[9] j3 differential o flashrom_cfg[0] bl15 gtl i flashrom_cfg[1] bm15 gtl i flashrom_cfg[2] bj15 gtl i flashrom_clk bl11 gtl od flashrom_cs_n[0] bk13 gtl od flashrom_cs_n[1] bm13 gtl od flashrom_cs_n[2] bl14 gtl od flashrom_cs_n[3] bm14 gtl od flashrom_dati bl12 gtl i flashrom_dato bm12 gtl od flashrom_wp_n bk11 gtl od force_pr_n c4 gtl i isense_dn b5 gtl i isense_dp a5 gtl i lt-sx (test-lo) bf10 gtl i mbp[0]_n g2 gtl io mbp[1]_n f2 gtl io mbp[2]_n f1 gtl io mbp[3]_n e2 gtl io mbp[4]_n f4 gtl io mbp[5]_n e3 gtl io mbp[6]_n e1 gtl io mbp[7]_n e4 gtl io mem_throttle0_n bc10 gtl i mem_throttle1_n bd10 gtl i nmi d5 gtl i peci d43 cmos io prdy_n c3 cmos o preq_n d3 cmos i proc_id[0] aw9 cmos o proc_id[1] ay9 cmos o prochot_n d2 gtl od psi_cache_n bf14 cmos o psi_n g7 cmos o pwrgood g41 cmos i qpi0_clkrx_dn bf37 scid diff. i qpi0_clkrx_dp bf36 scid diff. i qpi0_clktx_dn bl41 scid diff. o table 4-1. pin list, sorted by socket name (sheet 7 of 39) socket (emts) land # format io qpi0_clktx_dp bm41 scid diff. o qpi0_drx_dn[0] bb38 scid diff. i qpi0_drx_dn[1] ay41 scid diff. i qpi0_drx_dn[10] be35 scid diff. i qpi0_drx_dn[11] bg35 scid diff. i qpi0_drx_dn[12] bj33 scid diff. i qpi0_drx_dn[13] bm33 scid diff. i qpi0_drx_dn[14] bl32 scid diff. i qpi0_drx_dn[15] bh33 scid diff. i qpi0_drx_dn[16] bg33 scid diff. i qpi0_drx_dn[17] bf32 scid diff. i qpi0_drx_dn[18] be33 scid diff. i qpi0_drx_dn[19] bd34 scid diff. i qpi0_drx_dn[2] ba40 scid diff. i qpi0_drx_dn[3] bc39 scid diff. i qpi0_drx_dn[4] bc41 scid diff. i qpi0_drx_dn[5] bd40 scid diff. i qpi0_drx_dn[6] bc36 scid diff. i qpi0_drx_dn[7] bf40 scid diff. i qpi0_drx_dn[8] be39 scid diff. i qpi0_drx_dn[9] bd37 scid diff. i qpi0_drx_dp[0] bb39 scid diff. i qpi0_drx_dp[1] ba41 scid diff. i qpi0_drx_dp[10] bf35 scid diff. i qpi0_drx_dp[11] bg34 scid diff. i qpi0_drx_dp[12] bk33 scid diff. i qpi0_drx_dp[13] bm32 scid diff. i qpi0_drx_dp[14] bk32 scid diff. i qpi0_drx_dp[15] bh32 scid diff. i qpi0_drx_dp[16] bf33 scid diff. i qpi0_drx_dp[17] be32 scid diff. i qpi0_drx_dp[18] be34 scid diff. i qpi0_drx_dp[19] bd35 scid diff. i qpi0_drx_dp[2] bb40 scid diff. i qpi0_drx_dp[3] bc40 scid diff. i qpi0_drx_dp[4] bd41 scid diff. i qpi0_drx_dp[5] be40 scid diff. i qpi0_drx_dp[6] bd36 scid diff. i qpi0_drx_dp[7] bf39 scid diff. i qpi0_drx_dp[8] be38 scid diff. i qpi0_drx_dp[9] be37 scid diff. i table 4-1. pin list, sorted by socket name (sheet 8 of 39) socket (emts) land # format io
datasheet volume 1 of 2 69 pin listing qpi0_dtx_dn[0] bg42 scid diff. o qpi0_dtx_dn[1] bf43 scid diff. o qpi0_dtx_dn[10] bj41 scid diff. o qpi0_dtx_dn[11] bl40 scid diff. o qpi0_dtx_dn[12] bk39 scid diff. o qpi0_dtx_dn[13] bl37 scid diff. o qpi0_dtx_dn[14] bk37 scid diff. o qpi0_dtx_dn[15] bm36 scid diff. o qpi0_dtx_dn[16] bl35 scid diff. o qpi0_dtx_dn[17] bj36 scid diff. o qpi0_dtx_dn[18] bj37 scid diff. o qpi0_dtx_dn[19] bh39 scid diff. o qpi0_dtx_dn[2] bf44 scid diff. o qpi0_dtx_dn[3] bf46 scid diff. o qpi0_dtx_dn[4] bh43 scid diff. o qpi0_dtx_dn[5] bh45 scid diff. o qpi0_dtx_dn[6] bj43 scid diff. o qpi0_dtx_dn[7] bk45 scid diff. o qpi0_dtx_dn[8] bk42 scid diff. o qpi0_dtx_dn[9] bl43 scid diff. o qpi0_dtx_dp[0] bh42 scid diff. o qpi0_dtx_dp[1] bg43 scid diff. o qpi0_dtx_dp[10] bj40 scid diff. o qpi0_dtx_dp[11] bl39 scid diff. o qpi0_dtx_dp[12] bj39 scid diff. o qpi0_dtx_dp[13] bm37 scid diff. o qpi0_dtx_dp[14] bk36 scid diff. o qpi0_dtx_dp[15] bm35 scid diff. o qpi0_dtx_dp[16] bk35 scid diff. o qpi0_dtx_dp[17] bj35 scid diff. o qpi0_dtx_dp[18] bh37 scid diff. o qpi0_dtx_dp[19] bh40 scid diff. o qpi0_dtx_dp[2] bf45 scid diff. o qpi0_dtx_dp[3] bg46 scid diff. o qpi0_dtx_dp[4] bh44 scid diff. o qpi0_dtx_dp[5] bj45 scid diff. o qpi0_dtx_dp[6] bk43 scid diff. o qpi0_dtx_dp[7] bk44 scid diff. o qpi0_dtx_dp[8] bk41 scid diff. o qpi0_dtx_dp[9] bl42 scid diff. o qpi1_clkrx_dn ap41 scid diff. i table 4-1. pin list, sorted by socket name (sheet 9 of 39) socket (emts) land # format io qpi1_clkrx_dp ar41 scid diff. i qpi1_clktx_dn ay45 scid diff. o qpi1_clktx_dp ay46 scid diff. o qpi1_drx_dn[0] an38 scid diff. i qpi1_drx_dn[1] am37 scid diff. i qpi1_drx_dn[10] ar40 scid diff. i qpi1_drx_dn[11] au39 scid diff. i qpi1_drx_dn[12] au41 scid diff. i qpi1_drx_dn[13] av40 scid diff. i qpi1_drx_dn[14] aw39 scid diff. i qpi1_drx_dn[15] ay40 scid diff. i qpi1_drx_dn[16] av38 scid diff. i qpi1_drx_dn[17] ba38 scid diff. i qpi1_drx_dn[18] at39 scid diff. i qpi1_drx_dn[19] ar38 scid diff. i qpi1_drx_dn[2] aj37 scid diff. i qpi1_drx_dn[3] ak38 scid diff. i qpi1_drx_dn[4] ah41 scid diff. i qpi1_drx_dn[5] aj40 scid diff. i qpi1_drx_dn[6] al39 scid diff. i qpi1_drx_dn[7] al41 scid diff. i qpi1_drx_dn[8] am40 scid diff. i qpi1_drx_dn[9] ap39 scid diff. i qpi1_drx_dp[0] an39 scid diff. i qpi1_drx_dp[1] am38 scid diff. i qpi1_drx_dp[10] at40 scid diff. i qpi1_drx_dp[11] au40 scid diff. i qpi1_drx_dp[12] av41 scid diff. i qpi1_drx_dp[13] aw40 scid diff. i qpi1_drx_dp[14] aw38 scid diff. i qpi1_drx_dp[15] ay39 scid diff. i qpi1_drx_dp[16] av37 scid diff. i qpi1_drx_dp[17] ba37 scid diff. i qpi1_drx_dp[18] at38 scid diff. i qpi1_drx_dp[19] ar37 scid diff. i qpi1_drx_dp[2] aj38 scid diff. i qpi1_drx_dp[3] ak39 scid diff. i qpi1_drx_dp[4] aj41 scid diff. i qpi1_drx_dp[5] ak40 scid diff. i qpi1_drx_dp[6] al40 scid diff. i qpi1_drx_dp[7] am41 scid diff. i table 4-1. pin list, sorted by socket name (sheet 10 of 39) socket (emts) land # format io
pin listing 70 datasheet volume 1 of 2 qpi1_drx_dp[8] an40 scid diff. i qpi1_drx_dp[9] ap40 scid diff. i qpi1_dtx_dn[0] at43 scid diff. o qpi1_dtx_dn[1] ar43 scid diff. o qpi1_dtx_dn[10] ba44 scid diff. o qpi1_dtx_dn[11] ba46 scid diff. o qpi1_dtx_dn[12] bb44 scid diff. o qpi1_dtx_dn[13] bc45 scid diff. o qpi1_dtx_dn[14] bd45 scid diff. o qpi1_dtx_dn[15] bc43 scid diff. o qpi1_dtx_dn[16] be44 scid diff. o qpi1_dtx_dn[17] ba43 scid diff. o qpi1_dtx_dn[18] aw44 scid diff. o qpi1_dtx_dn[19] av43 scid diff. o qpi1_dtx_dn[2] an43 scid diff. o qpi1_dtx_dn[3] am45 scid diff. o qpi1_dtx_dn[4] ap45 scid diff. o qpi1_dtx_dn[5] ar44 scid diff. o qpi1_dtx_dn[6] ar46 scid diff. o qpi1_dtx_dn[7] au45 scid diff. o qpi1_dtx_dn[8] av44 scid diff. o qpi1_dtx_dn[9] av46 scid diff. o qpi1_dtx_dp[0] at44 scid diff. o qpi1_dtx_dp[1] ap43 scid diff. o qpi1_dtx_dp[10] ba45 scid diff. o qpi1_dtx_dp[11] bb46 scid diff. o qpi1_dtx_dp[12] bb43 scid diff. o qpi1_dtx_dp[13] bc44 scid diff. o qpi1_dtx_dp[14] be45 scid diff. o qpi1_dtx_dp[15] bd43 scid diff. o qpi1_dtx_dp[16] be43 scid diff. o qpi1_dtx_dp[17] ay43 scid diff. o qpi1_dtx_dp[18] aw43 scid diff. o qpi1_dtx_dp[19] au43 scid diff. o qpi1_dtx_dp[2] an44 scid diff. o qpi1_dtx_dp[3] am44 scid diff. o qpi1_dtx_dp[4] ap46 scid diff. o qpi1_dtx_dp[5] ar45 scid diff. o qpi1_dtx_dp[6] at46 scid diff. o qpi1_dtx_dp[7] au46 scid diff. o qpi1_dtx_dp[8] av45 scid diff. o table 4-1. pin list, sorted by socket name (sheet 11 of 39) socket (emts) land # format io qpi1_dtx_dp[9] aw46 scid diff. o qpi2_clkrx_dn ab40 scid diff. i qpi2_clkrx_dp ab39 scid diff. i qpi2_clktx_dn ae44 scid diff. o qpi2_clktx_dp ae45 scid diff. o qpi2_drx_dn[0] ac37 scid diff. i qpi2_drx_dn[1] ad38 scid diff. i qpi2_drx_dn[10] aa40 scid diff. i qpi2_drx_dn[11] y41 scid diff. i qpi2_drx_dn[12] w40 scid diff. i qpi2_drx_dn[13] v40 scid diff. i qpi2_drx_dn[14] u41 scid diff. i qpi2_drx_dn[15] t40 scid diff. i qpi2_drx_dn[16] v39 scid diff. i qpi2_drx_dn[17] v37 scid diff. i qpi2_drx_dn[18] y38 scid diff. i qpi2_drx_dn[19] aa37 scid diff. i qpi2_drx_dn[2] af37 scid diff. i qpi2_drx_dn[3] ag38 scid diff. i qpi2_drx_dn[4] ah40 scid diff. i qpi2_drx_dn[5] ag40 scid diff. i qpi2_drx_dn[6] af41 scid diff. i qpi2_drx_dn[7] ae40 scid diff. i qpi2_drx_dn[8] ad40 scid diff. i qpi2_drx_dn[9] ac41 scid diff. i qpi2_drx_dp[0] ac38 scid diff. i qpi2_drx_dp[1] ad39 scid diff. i qpi2_drx_dp[10] y40 scid diff. i qpi2_drx_dp[11] w41 scid diff. i qpi2_drx_dp[12] w39 scid diff. i qpi2_drx_dp[13] u40 scid diff. i qpi2_drx_dp[14] t41 scid diff. i qpi2_drx_dp[15] t39 scid diff. i qpi2_drx_dp[16] v38 scid diff. i qpi2_drx_dp[17] u37 scid diff. i qpi2_drx_dp[18] y37 scid diff. i qpi2_drx_dp[19] ab37 scid diff. i qpi2_drx_dp[2] af38 scid diff. i qpi2_drx_dp[3] ag39 scid diff. i qpi2_drx_dp[4] ah39 scid diff. i qpi2_drx_dp[5] af40 scid diff. i table 4-1. pin list, sorted by socket name (sheet 12 of 39) socket (emts) land # format io
datasheet volume 1 of 2 71 pin listing qpi2_drx_dp[6] ae41 scid diff. i qpi2_drx_dp[7] ae39 scid diff. i qpi2_drx_dp[8] ac40 scid diff. i qpi2_drx_dp[9] ab41 scid diff. i qpi2_dtx_dn[0] ae43 scid diff. o qpi2_dtx_dn[1] ah43 scid diff. o qpi2_dtx_dn[10] ad43 scid diff. o qpi2_dtx_dn[11] ad46 scid diff. o qpi2_dtx_dn[12] ac45 scid diff. o qpi2_dtx_dn[13] ab46 scid diff. o qpi2_dtx_dn[14] aa45 scid diff. o qpi2_dtx_dn[15] y46 scid diff. o qpi2_dtx_dn[16] w45 scid diff. o qpi2_dtx_dn[17] aa44 scid diff. o qpi2_dtx_dn[18] w43 scid diff. o qpi2_dtx_dn[19] ab43 scid diff. o qpi2_dtx_dn[2] am43 scid diff. o qpi2_dtx_dn[3] an46 scid diff. o qpi2_dtx_dn[4] al45 scid diff. o qpi2_dtx_dn[5] ak43 scid diff. o qpi2_dtx_dn[6] ak45 scid diff. o qpi2_dtx_dn[7] ah44 scid diff. o qpi2_dtx_dn[8] ag43 scid diff. o qpi2_dtx_dn[9] ag45 scid diff. o qpi2_dtx_dp[0] af43 scid diff. o qpi2_dtx_dp[1] aj43 scid diff. o qpi2_dtx_dp[10] ad44 scid diff. o qpi2_dtx_dp[11] ac46 scid diff. o qpi2_dtx_dp[12] ac44 scid diff. o qpi2_dtx_dp[13] ab45 scid diff. o qpi2_dtx_dp[14] y45 scid diff. o qpi2_dtx_dp[15] w46 scid diff. o qpi2_dtx_dp[16] w44 scid diff. o qpi2_dtx_dp[17] aa43 scid diff. o qpi2_dtx_dp[18] y43 scid diff. o qpi2_dtx_dp[19] ac43 scid diff. o qpi2_dtx_dp[2] al43 scid diff. o qpi2_dtx_dp[3] am46 scid diff. o qpi2_dtx_dp[4] al46 scid diff. o qpi2_dtx_dp[5] ak44 scid diff. o qpi2_dtx_dp[6] aj45 scid diff. o table 4-1. pin list, sorted by socket name (sheet 13 of 39) socket (emts) land # format io qpi2_dtx_dp[7] ah45 scid diff. o qpi2_dtx_dp[8] ag44 scid diff. o qpi2_dtx_dp[9] af45 scid diff. o qpi3_clkrx_dn n45 scid diff. i qpi3_clkrx_dp m45 scid diff. i qpi3_clktx_dn e44 scid diff. o qpi3_clktx_dp d44 scid diff. o qpi3_drx_dn[0] p41 scid diff. i qpi3_drx_dn[1] n41 scid diff. i qpi3_drx_dn[10] n43 scid diff. i qpi3_drx_dn[11] l44 scid diff. i qpi3_drx_dn[12] l43 scid diff. i qpi3_drx_dn[13] m41 scid diff. i qpi3_drx_dn[14] n40 scid diff. i qpi3_drx_dn[15] l40 scid diff. i qpi3_drx_dn[16] m38 scid diff. i qpi3_drx_dn[17] n38 scid diff. i qpi3_drx_dn[18] p40 scid diff. i qpi3_drx_dn[19] r39 scid diff. i qpi3_drx_dn[2] t42 scid diff. i qpi3_drx_dn[3] u43 scid diff. i qpi3_drx_dn[4] u44 scid diff. i qpi3_drx_dn[5] r43 scid diff. i qpi3_drx_dn[6] u46 scid diff. i qpi3_drx_dn[7] t45 scid diff. i qpi3_drx_dn[8] p44 scid diff. i qpi3_drx_dn[9] p46 scid diff. i qpi3_drx_dp[0] r41 scid diff. i qpi3_drx_dp[1] n42 scid diff. i qpi3_drx_dp[10] m43 scid diff. i qpi3_drx_dp[11] m44 scid diff. i qpi3_drx_dp[12] l42 scid diff. i qpi3_drx_dp[13] l41 scid diff. i qpi3_drx_dp[14] m40 scid diff. i qpi3_drx_dp[15] l39 scid diff. i qpi3_drx_dp[16] l38 scid diff. i qpi3_drx_dp[17] n37 scid diff. i qpi3_drx_dp[18] p39 scid diff. i qpi3_drx_dp[19] r38 scid diff. i qpi3_drx_dp[2] r42 scid diff. i qpi3_drx_dp[3] t43 scid diff. i table 4-1. pin list, sorted by socket name (sheet 14 of 39) socket (emts) land # format io
pin listing 72 datasheet volume 1 of 2 qpi3_drx_dp[4] u45 scid diff. i qpi3_drx_dp[5] r44 scid diff. i qpi3_drx_dp[6] t46 scid diff. i qpi3_drx_dp[7] r45 scid diff. i qpi3_drx_dp[8] p45 scid diff. i qpi3_drx_dp[9] n46 scid diff. i qpi3_dtx_dn[0] j40 scid diff. o qpi3_dtx_dn[1] h42 scid diff. o qpi3_dtx_dn[10] c45 scid diff. o qpi3_dtx_dn[11] b44 scid diff. o qpi3_dtx_dn[12] f42 scid diff. o qpi3_dtx_dn[13] b42 scid diff. o qpi3_dtx_dn[14] a41 scid diff. o qpi3_dtx_dn[15] d42 scid diff. o qpi3_dtx_dn[16] c39 scid diff. o qpi3_dtx_dn[17] f41 scid diff. o qpi3_dtx_dn[18] e39 scid diff. o qpi3_dtx_dn[19] e40 scid diff. o qpi3_dtx_dn[2] g43 scid diff. o qpi3_dtx_dn[3] j43 scid diff. o qpi3_dtx_dn[4] f43 scid diff. o qpi3_dtx_dn[5] k46 scid diff. o qpi3_dtx_dn[6] j45 scid diff. o qpi3_dtx_dn[7] g44 scid diff. o qpi3_dtx_dn[8] g46 scid diff. o qpi3_dtx_dn[9] e45 scid diff. o qpi3_dtx_dp[0] j41 scid diff. o qpi3_dtx_dp[1] j42 scid diff. o qpi3_dtx_dp[10] c44 scid diff. o qpi3_dtx_dp[11] b43 scid diff. o qpi3_dtx_dp[12] e42 scid diff. o qpi3_dtx_dp[13] c42 scid diff. o qpi3_dtx_dp[14] b41 scid diff. o qpi3_dtx_dp[15] d41 scid diff. o qpi3_dtx_dp[16] c40 scid diff. o qpi3_dtx_dp[17] f40 scid diff. o qpi3_dtx_dp[18] f39 scid diff. o qpi3_dtx_dp[19] d40 scid diff. o qpi3_dtx_dp[2] h43 scid diff. o qpi3_dtx_dp[3] j44 scid diff. o qpi3_dtx_dp[4] f44 scid diff. o table 4-1. pin list, sorted by socket name (sheet 15 of 39) socket (emts) land # format io qpi3_dtx_dp[5] j46 scid diff. o qpi3_dtx_dp[6] h45 scid diff. o qpi3_dtx_dp[7] g45 scid diff. o qpi3_dtx_dp[8] f46 scid diff. o qpi3_dtx_dp[9] e46 scid diff. o reset_n b4 gtl i rsvd aa10 io rsvd aa2 io rsvd ab3 io rsvd ad37 io rsvd ae38 io rsvd af10 io rsvd ag10 io rsvd ag37 io rsvd ag5 io rsvd ag6 io rsvd ag7 io rsvd ag9 io rsvd ah10 io rsvd ah3 io rsvd ah38 io rsvd ah4 io rsvd ah5 io rsvd ah7 io rsvd ah8 io rsvd ah9 io rsvd aj4 io rsvd aj46 io rsvd aj5 io rsvd aj6 io rsvd aj7 io rsvd aj8 io rsvd aj9 io rsvd ak37 io rsvd ak6 io rsvd ak8 io rsvd ak9 io rsvd al38 io rsvd al6 io rsvd al8 io rsvd am10 io table 4-1. pin list, sorted by socket name (sheet 16 of 39) socket (emts) land # format io
datasheet volume 1 of 2 73 pin listing rsvd am6 io rsvd am7 io rsvd am8 io rsvd am9 io rsvd an37 io rsvd ap38 io rsvd at2 io rsvd at37 io rsvd au2 io rsvd au38 io rsvd aw37 io rsvd ay38 io rsvd b46 io rsvd bc35 io rsvd bc38 io rsvd bc9 io rsvd bd12 io rsvd bd13 io rsvd bd38 io rsvd bd9 io rsvd bf12 io rsvd bf3 o rsvd bg2 o rsvd bg32 o rsvd bg45 o rsvd bh15 o rsvd bh16 o rsvd c46 o rsvd d4 o rsvd g6 o rsvd h9 o rsvd j9 o rsvd m39 o rsvd p37 o rsvd p38 o rsvd p9 o rsvd r9 o rsvd w38 o rsvd w9 io rsvd y10 io rsvd y9 io table 4-1. pin list, sorted by socket name (sheet 17 of 39) socket (emts) land # format io runbist bj10 gtl i sktdis_n bg11 gtl i sktid[0] bk14 cmos i sktid[1] bj14 cmos i sktid[2] bh14 cmos i sktocc_n bj13 o sm_wp bk12 cmos i smbclk bj12 cmos i/od smbdat bh12 cmos i/od spdclk bg10 cmos i/od spddat bg9 cmos i/od sysclk_dn t38 differential i sysclk_dp u38 differential i sysclk_lai aa39 differential i sysclk_lai_n aa38 differential i tclk k10 gtl i tdi l9 gtl i tdo l10 gtl-od o test[0] a1 i test[1] a46 io test[2] bm46 i test[3] bm1 io tes t- h i ap10 gtl i thermalert_n bg13 cmos od thermtrip_n f5 gtl-od o tms m9 gtl i trst_n m10 gtl i vcache bc15 power i vcache bc17 power i vcache bc18 power i vcache bc20 power i vcache bc21 power i vcache bc23 power i vcache bc24 power i vcache bc26 power i vcache bc27 power i vcache bc29 power i vcache bc30 power i vcache bc32 power i vcache bc33 power i vcache bd15 power i table 4-1. pin list, sorted by socket name (sheet 18 of 39) socket (emts) land # format io
pin listing 74 datasheet volume 1 of 2 vcache bd17 power i vcache bd18 power i vcache bd20 power i vcache bd21 power i vcache bd23 power i vcache bd24 power i vcache bd26 power i vcache bd27 power i vcache bd29 power i vcache bd30 power i vcache bd32 power i vcache bd33 power i vcache be15 power i vcache be17 power i vcache be18 power i vcache be20 power i vcache be21 power i vcache be23 power i vcache be24 power i vcache be26 power i vcache be27 power i vcache be29 power i vcache be30 power i vcache bf15 power i vcache bf17 power i vcache bf18 power i vcache bf20 power i vcache bf27 power i vcache bf29 power i vcache bf30 power i vcache bg15 power i vcache bg17 power i vcache bg18 power i vcache bg20 power i vcache bg27 power i vcache bg29 power i vcache bg30 power i vcache bh17 power i vcache bh18 power i vcache bh20 power i vcache bh27 power i table 4-1. pin list, sorted by socket name (sheet 19 of 39) socket (emts) land # format io vcache bh29 power i vcache bh30 power i vcache bj18 power i vcache bj20 power i vcache bj21 power i vcache bj23 power i vcache bj24 power i vcache bj26 power i vcache bj27 power i vcache bj29 power i vcache bj30 power i vcache bk20 power i vcache bk21 power i vcache bk23 power i vcache bk24 power i vcache bk26 power i vcache bk27 power i vcache bk29 power i vcache bk30 power i vcache bl20 power i vcache bl21 power i vcache bl23 power i vcache bl24 power i vcache bl26 power i vcache bl27 power i vcache bl29 power i vcache bl30 power i vcache bm20 power i vcache bm21 power i vcache bm26 power i vcache bm27 power i vcache bm29 power i vcache bm30 power i vcachesense bk18 power io vcc33 be10 power i vcc33 be11 power i vcc33 be12 power i vcccore k38 power i vcccore k37 power i vcccore k35 power i vcccore k34 power i table 4-1. pin list, sorted by socket name (sheet 20 of 39) socket (emts) land # format io
datasheet volume 1 of 2 75 pin listing vcccore k32 power i vcccore k31 power i vcccore k29 power i vcccore k28 power i vcccore k26 power i vcccore k25 power i vcccore k22 power i vcccore k21 power i vcccore k19 power i vcccore k18 power i vcccore k16 power i vcccore k15 power i vcccore k13 power i vcccore k12 power i vcccore j38 power i vcccore j37 power i vcccore j35 power i vcccore j34 power i vcccore j32 power i vcccore j31 power i vcccore j29 power i vcccore j28 power i vcccore j26 power i vcccore j25 power i vcccore j22 power i vcccore j21 power i vcccore j19 power i vcccore j18 power i vcccore j16 power i vcccore j15 power i vcccore j13 power i vcccore j12 power i vcccore j10 power i vcccore h38 power i vcccore h37 power i vcccore h35 power i vcccore h34 power i vcccore h32 power i vcccore h31 power i vcccore h29 power i vcccore h28 power i table 4-1. pin list, sorted by socket name (sheet 21 of 39) socket (emts) land # format io vcccore h26 power i vcccore h25 power i vcccore h22 power i vcccore h21 power i vcccore h19 power i vcccore h18 power i vcccore h16 power i vcccore h15 power i vcccore h13 power i vcccore h12 power i vcccore h10 power i vcccore g38 power i vcccore g37 power i vcccore g35 power i vcccore g34 power i vcccore g32 power i vcccore g31 power i vcccore g29 power i vcccore g28 power i vcccore g19 power i vcccore g18 power i vcccore g16 power i vcccore g15 power i vcccore g13 power i vcccore g12 power i vcccore g10 power i vcccore g9 power i vcccore f38 power i vcccore f37 power i vcccore f35 power i vcccore f34 power i vcccore f32 power i vcccore f31 power i vcccore f29 power i vcccore f28 power i vcccore f19 power i vcccore f18 power i vcccore f16 power i vcccore f15 power i vcccore f13 power i vcccore f12 power i table 4-1. pin list, sorted by socket name (sheet 22 of 39) socket (emts) land # format io
pin listing 76 datasheet volume 1 of 2 vcccore f10 power i vcccore f9 power i vcccore e38 power i vcccore e37 power i vcccore e35 power i vcccore e34 power i vcccore e32 power i vcccore e31 power i vcccore e29 power i vcccore e28 power i vcccore e19 power i vcccore e18 power i vcccore e16 power i vcccore e15 power i vcccore e13 power i vcccore e12 power i vcccore e10 power i vcccore e9 power i vcccore d38 power i vcccore d37 power i vcccore d35 power i vcccore d34 power i vcccore d32 power i vcccore d31 power i vcccore d29 power i vcccore d28 power i vcccore d26 power i vcccore d25 power i vcccore d22 power i vcccore d21 power i vcccore d19 power i vcccore d18 power i vcccore d16 power i vcccore d15 power i vcccore d13 power i vcccore d12 power i vcccore d10 power i vcccore d9 power i vcccore c38 power i vcccore c37 power i vcccore c35 power i table 4-1. pin list, sorted by socket name (sheet 23 of 39) socket (emts) land # format io vcccore c34 power i vcccore c32 power i vcccore c31 power i vcccore c29 power i vcccore c28 power i vcccore c26 power i vcccore c25 power i vcccore c22 power i vcccore c21 power i vcccore c19 power i vcccore c18 power i vcccore c16 power i vcccore c15 power i vcccore c13 power i vcccore c12 power i vcccore c10 power i vcccore c9 power i vcccore b38 power i vcccore b37 power i vcccore b35 power i vcccore b34 power i vcccore b32 power i vcccore b31 power i vcccore b29 power i vcccore b28 power i vcccore b26 power i vcccore b25 power i vcccore b22 power i vcccore b21 power i vcccore b19 power i vcccore b18 power i vcccore b16 power i vcccore b15 power i vcccore b13 power i vcccore b12 power i vcccore b10 power i vcccore b9 power i vcccore a38 power i vcccore a37 power i vcccore a35 power i vcccore a34 power i table 4-1. pin list, sorted by socket name (sheet 24 of 39) socket (emts) land # format io
datasheet volume 1 of 2 77 pin listing vcccore a32 power i vcccore a31 power i vcccore a29 power i vcccore a28 power i vcccore a26 power i vcccore a21 power i vcccore a19 power i vcccore a18 power i vcccore a16 power i vcccore a15 power i vcccore a13 power i vcccore a12 power i vcccore a10 power i vcccore a9 power i vcoresense f7 power io vid[0] e7 cmos io vid[1] e6 cmos io vid[2] d7 cmos io vid[3] d6 cmos io vid[4] c7 cmos io vid[5] c6 cmos io vid[6] b7 cmos io vid[7] a6 cmos io vio_vid[1] bh38 cmos o vio_vid[2] bk38 cmos o vio_vid[3] bm38 cmos o vio_vid[4] bm39 cmos o vioc aa42 power i vioc ac36 power i vioc ac42 power i vioc ad42 power i vioc af36 power i vioc af42 power i vioc ag42 power i vioc aj36 power i vioc aj42 power i vioc ak42 power i vioc am36 power i vioc am42 power i vioc an42 power i vioc ar36 power i table 4-1. pin list, sorted by socket name (sheet 25 of 39) socket (emts) land # format io vioc ar42 power i vioc at42 power i vioc av36 power i vioc av42 power i vioc aw42 power i vioc ba36 power i vioc ba42 power i vioc bb37 power i vioc bb42 power i vioc bd42 power i vioc be42 power i vioc bf41 power i vioc bg36 power i vioc bg37 power i vioc bg38 power i vioc bg39 power i vioc bg41 power i vioc bh34 power i vioc bh35 power i vioc bh41 power i vioc bk34 power i vioc bl34 power i vioc m36 power i vioc p36 power i vioc u36 power i vioc v42 power i vioc v43 power i vioc v44 power i vioc v45 power i vioc y36 power i vioc y42 power i viof ab9 power i viof ac10 power i viof ac11 power i viof ae9 power i viof af11 power i viof aj10 power i viof aj11 power i viof al10 power i viof am11 power i viof an10 power i table 4-1. pin list, sorted by socket name (sheet 26 of 39) socket (emts) land # format io
pin listing 78 datasheet volume 1 of 2 viof an8 power i viof ap9 power i viof ar10 power i viof ar11 power i viof at9 power i viof au9 power i viof av10 power i viof av11 power i viof ba1 power i viof ba10 power i viof ba11 power i viof ba2 power i viof ba3 power i viof ba7 power i viof ba8 power i viof bb10 power i viof bb11 power i viof bb2 power i viof bb4 power i viof bb5 power i viof bb6 power i viof bb8 power i viof p10 power i viof p11 power i viof r10 power i viof r11 power i viof t1 power i viof t2 power i viof t4 power i viof t6 power i viof t7 power i viof t8 power i viof u1 power i viof u10 power i viof u11 power i viof u5 power i viof u8 power i viof u9 power i viof y11 power i viopwrgood h41 cmos i vreg aj2 power i table 4-1. pin list, sorted by socket name (sheet 27 of 39) socket (emts) land # format io vreg ak1 power i vreg ak2 power i vreg ak3 power i vreg ak4 power i vreg al1 power i vreg al2 power i vreg al3 power i vreg al4 power i vreg al5 power i vss a11 gnd i vss a14 gnd i vss a17 gnd i vss a2 gnd i vss a20 gnd i vss a27 gnd i vss a3 gnd i vss a30 gnd i vss a33 gnd i vss a36 gnd i vss a39 gnd i vss a4 gnd i vss a40 gnd i vss a42 gnd i vss a43 gnd i vss a44 gnd i vss a45 gnd i vss a7 gnd i vss a8 gnd i vss aa11 gnd i vss aa3 gnd i vss aa36 gnd i vss aa41 gnd i vss aa46 gnd i vss aa5 gnd i vss aa9 gnd i vss ab10 gnd i vss ab11 gnd i vss ab36 gnd i vss ab38 gnd i vss ab42 gnd i vss ab44 gnd i table 4-1. pin list, sorted by socket name (sheet 28 of 39) socket (emts) land # format io
datasheet volume 1 of 2 79 pin listing vss ab7 gnd i vss ac1 gnd i vss ac39 gnd i vss ac4 gnd i vss ac9 gnd i vss ad10 gnd i vss ad11 gnd i vss ad36 gnd i vss ad41 gnd i vss ad45 gnd i vss ad5 gnd i vss ad7 gnd i vss ae10 gnd i vss ae11 gnd i vss ae3 gnd i vss ae36 gnd i vss ae37 gnd i vss ae42 gnd i vss ae7 gnd i vss af39 gnd i vss af44 gnd i vss af9 gnd i vss ag11 gnd i vss ag36 gnd i vss ag4 gnd i vss ag41 gnd i vss ag8 gnd i vss ah11 gnd i vss ah2 gnd i vss ah36 gnd i vss ah37 gnd i vss ah42 gnd i vss ah6 gnd i vss aj1 gnd i vss aj3 gnd i vss aj39 gnd i vss aj44 gnd i vss ak10 gnd i vss ak11 gnd i vss ak36 gnd i vss ak41 gnd i table 4-1. pin list, sorted by socket name (sheet 29 of 39) socket (emts) land # format io vss ak46 gnd i vss ak5 gnd i vss ak7 gnd i vss al11 gnd i vss al36 gnd i vss al37 gnd i vss al42 gnd i vss al44 gnd i vss al7 gnd i vss al9 gnd i vss am2 gnd i vss am3 gnd i vss am39 gnd i vss am5 gnd i vss an11 gnd i vss an3 gnd i vss an36 gnd i vss an41 gnd i vss an45 gnd i vss an7 gnd i vss an9 gnd i vss ap1 gnd i vss ap11 gnd i vss ap36 gnd i vss ap37 gnd i vss ap4 gnd i vss ap42 gnd i vss ap44 gnd i vss ap5 gnd i vss ar39 gnd i vss ar5 gnd i vss ar7 gnd i vss ar9 gnd i vss at1 gnd i vss at10 gnd i vss at11 gnd i vss at3 gnd i vss at36 gnd i vss at41 gnd i vss at45 gnd i vss au1 gnd i table 4-1. pin list, sorted by socket name (sheet 30 of 39) socket (emts) land # format io
pin listing 80 datasheet volume 1 of 2 vss au10 gnd i vss au11 gnd i vss au36 gnd i vss au37 gnd i vss au42 gnd i vss au44 gnd i vss au6 gnd i vss au8 gnd i vss av39 gnd i vss av5 gnd i vss av9 gnd i vss aw10 gnd i vss aw11 gnd i vss aw3 gnd i vss aw36 gnd i vss aw41 gnd i vss aw45 gnd i vss aw7 gnd i vss ay1 gnd i vss ay10 gnd i vss ay11 gnd i vss ay36 gnd i vss ay37 gnd i vss ay42 gnd i vss ay44 gnd i vss ay6 gnd i vss b1 gnd i vss b11 gnd i vss b14 gnd i vss b17 gnd i vss b2 gnd i vss b20 gnd i vss b23 gnd i vss b24 gnd i vss b27 gnd i vss b3 gnd i vss b30 gnd i vss b33 gnd i vss b36 gnd i vss b39 gnd i vss b40 gnd i table 4-1. pin list, sorted by socket name (sheet 31 of 39) socket (emts) land # format io vss b45 gnd i vss b6 gnd i vss b8 gnd i vss ba39 gnd i vss ba4 gnd i vss ba9 gnd i vss bb3 gnd i vss bb36 gnd i vss bb41 gnd i vss bb45 gnd i vss bb7 gnd i vss bb9 gnd i vss bc11 gnd i vss bc12 gnd i vss bc13 gnd i vss bc14 gnd i vss bc16 gnd i vss bc19 gnd i vss bc22 gnd i vss bc25 gnd i vss bc28 gnd i vss bc31 gnd i vss bc34 gnd i vss bc37 gnd i vss bc42 gnd i vss bc5 gnd i vss bd11 gnd i vss bd14 gnd i vss bd16 gnd i vss bd19 gnd i vss bd22 gnd i vss bd25 gnd i vss bd28 gnd i vss bd3 gnd i vss bd31 gnd i vss bd39 gnd i vss bd44 gnd i vss bd7 gnd i vss be1 gnd i vss be13 gnd i vss be14 gnd i table 4-1. pin list, sorted by socket name (sheet 32 of 39) socket (emts) land # format io
datasheet volume 1 of 2 81 pin listing vss be16 gnd i vss be19 gnd i vss be22 gnd i vss be25 gnd i vss be28 gnd i vss be31 gnd i vss be36 gnd i vss be41 gnd i vss be46 gnd i vss be9 gnd i vss bf11 gnd i vss bf13 gnd i vss bf16 gnd i vss bf19 gnd i vss bf28 gnd i vss bf31 gnd i vss bf34 gnd i vss bf38 gnd i vss bf42 gnd i vss bf5 gnd i vss bf7 gnd i vss bg12 gnd i vss bg14 gnd i vss bg16 gnd i vss bg19 gnd i vss bg28 gnd i vss bg3 gnd i vss bg31 gnd i vss bg40 gnd i vss bg44 gnd i vss bg7 gnd i vss bh13 gnd i vss bh19 gnd i vss bh28 gnd i vss bh31 gnd i vss bh36 gnd i vss bh46 gnd i vss bh9 gnd i vss bj1 gnd i vss bj11 gnd i vss bj17 gnd i table 4-1. pin list, sorted by socket name (sheet 33 of 39) socket (emts) land # format io vss bj19 gnd i vss bj22 gnd i vss bj25 gnd i vss bj28 gnd i vss bj3 gnd i vss bj31 gnd i vss bj32 gnd i vss bj34 gnd i vss bj38 gnd i vss bj42 gnd i vss bj44 gnd i vss bj46 gnd i vss bj5 gnd i vss bj7 gnd i vss bk1 gnd i vss bk15 gnd i vss bk19 gnd i vss bk22 gnd i vss bk25 gnd i vss bk28 gnd i vss bk31 gnd i vss bk40 gnd i vss bk46 gnd i vss bk7 gnd i vss bl1 gnd i vss bl13 gnd i vss bl19 gnd i vss bl2 gnd i vss bl22 gnd i vss bl25 gnd i vss bl28 gnd i vss bl3 gnd i vss bl31 gnd i vss bl33 gnd i vss bl36 gnd i vss bl38 gnd i vss bl4 gnd i vss bl44 gnd i vss bl45 gnd i vss bl46 gnd i vss bl9 gnd i table 4-1. pin list, sorted by socket name (sheet 34 of 39) socket (emts) land # format io
pin listing 82 datasheet volume 1 of 2 vss bm11 gnd i vss bm16 gnd i vss bm19 gnd i vss bm2 gnd i vss bm28 gnd i vss bm3 gnd i vss bm31 gnd i vss bm34 gnd i vss bm4 gnd i vss bm40 gnd i vss bm42 gnd i vss bm43 gnd i vss bm44 gnd i vss bm45 gnd i vss bm7 gnd i vss c1 gnd i vss c11 gnd i vss c14 gnd i vss c17 gnd i vss c2 gnd i vss c20 gnd i vss c23 gnd i vss c24 gnd i vss c27 gnd i vss c30 gnd i vss c33 gnd i vss c36 gnd i vss c41 gnd i vss c43 gnd i vss c5 gnd i vss c8 gnd i vss d1 gnd i vss d11 gnd i vss d14 gnd i vss d17 gnd i vss d20 gnd i vss d23 gnd i vss d24 gnd i vss d27 gnd i vss d30 gnd i vss d33 gnd i table 4-1. pin list, sorted by socket name (sheet 35 of 39) socket (emts) land # format io vss d36 gnd i vss d39 gnd i vss d45 gnd i vss d46 gnd i vss d8 gnd i vss e11 gnd i vss e14 gnd i vss e17 gnd i vss e20 gnd i vss e27 gnd i vss e30 gnd i vss e33 gnd i vss e36 gnd i vss e41 gnd i vss e43 gnd i vss e5 gnd i vss e8 gnd i vss f11 gnd i vss f14 gnd i vss f17 gnd i vss f20 gnd i vss f27 gnd i vss f3 gnd i vss f30 gnd i vss f33 gnd i vss f36 gnd i vss f45 gnd i vss f8 gnd i vss g1 gnd i vss g11 gnd i vss g14 gnd i vss g17 gnd i vss g20 gnd i vss g27 gnd i vss g30 gnd i vss g33 gnd i vss g36 gnd i vss g39 gnd i vss g40 gnd i vss g42 gnd i vss g5 gnd i table 4-1. pin list, sorted by socket name (sheet 36 of 39) socket (emts) land # format io
datasheet volume 1 of 2 83 pin listing vss g8 gnd i vss h11 gnd i vss h14 gnd i vss h17 gnd i vss h20 gnd i vss h23 gnd i vss h24 gnd i vss h27 gnd i vss h30 gnd i vss h33 gnd i vss h36 gnd i vss h39 gnd i vss h4 gnd i vss h40 gnd i vss h44 gnd i vss h46 gnd i vss h8 gnd i vss j11 gnd i vss j14 gnd i vss j17 gnd i vss j2 gnd i vss j20 gnd i vss j23 gnd i vss j24 gnd i vss j27 gnd i vss j30 gnd i vss j33 gnd i vss j36 gnd i vss j39 gnd i vss j7 gnd i vss k11 gnd i vss k14 gnd i vss k17 gnd i vss k20 gnd i vss k23 gnd i vss k24 gnd i vss k27 gnd i vss k30 gnd i vss k33 gnd i vss k36 gnd i vss k39 gnd i table 4-1. pin list, sorted by socket name (sheet 37 of 39) socket (emts) land # format io vss k40 gnd i vss k41 gnd i vss k42 gnd i vss k43 gnd i vss k44 gnd i vss k45 gnd i vss k5 gnd i vss k7 gnd i vss k9 gnd i vss l11 gnd i vss l3 gnd i vss l36 gnd i vss l37 gnd i vss l4 gnd i vss l45 gnd i vss l46 gnd i vss l6 gnd i vss m1 gnd i vss m11 gnd i vss m2 gnd i vss m37 gnd i vss m42 gnd i vss m46 gnd i vss m8 gnd i vss n10 gnd i vss n11 gnd i vss n36 gnd i vss n39 gnd i vss n44 gnd i vss n5 gnd i vss n9 gnd i vss p3 gnd i vss p42 gnd i vss p43 gnd i vss p7 gnd i vss r1 gnd i vss r36 gnd i vss r37 gnd i vss r40 gnd i vss r46 gnd i vss t10 gnd i table 4-1. pin list, sorted by socket name (sheet 38 of 39) socket (emts) land # format io
pin listing 84 datasheet volume 1 of 2 vss t11 gnd i vss t3 gnd i vss t36 gnd i vss t37 gnd i vss t44 gnd i vss t5 gnd i vss t9 gnd i vss u2 gnd i vss u39 gnd i vss u42 gnd i vss u7 gnd i vss v10 gnd i vss v11 gnd i vss v36 gnd i vss v41 gnd i vss v46 gnd i vss v5 gnd i vss v9 gnd i vss w10 gnd i vss w11 gnd i vss w3 gnd i vss w36 gnd i vss w37 gnd i vss w42 gnd i vss w6 gnd i vss w7 gnd i vss y1 gnd i vss y39 gnd i vss y44 gnd i vsscachesense bk17 power io vsscoresense f6 power io table 4-1. pin list, sorted by socket name (sheet 39 of 39) socket (emts) land # format io
datasheet volume 1 of 2 85 pin listing 4.1.2 processor pin list, sorted by land number table 4-2. pin list, sorted by land number (sheet 1 of 39) land # socket (emts) format io a1 test[0] i a10 vcccore power i a11 vss gnd i a12 vcccore power i a13 vcccore power i a14 vss gnd i a15 vcccore power i a16 vcccore power i a17 vss gnd i a18 vcccore power i a19 vcccore power i a2 vss gnd i a20 vss gnd i a21 vcccore power i a26 vcccore power i a27 vss gnd i a28 vcccore power i a29 vcccore power i a3 vss gnd i a30 vss gnd i a31 vcccore power i a32 vcccore power i a33 vss gnd i a34 vcccore power i a35 vcccore power i a36 vss gnd i a37 vcccore power i a38 vcccore power i a39 vss gnd i a4 vss gnd i a40 vss gnd i a41 qpi3_dtx_dn[14] scid diff. o a42 vss gnd i a43 vss gnd i a44 vss gnd i a45 vss gnd i a46 test[1] io a5 isense_dp gtl i a6 vid[7] cmos io a7 vss gnd i a8 vss gnd i a9 vcccore powerf i aa1 fbd1nbidn[12] differential i aa10 rsvd io aa11 vss gnd i aa2 rsvd io aa3 vss gnd i aa36 vss gnd i aa37 qpi2_drx_dn[19] scid diff. i aa38 sysclk_lai_n differential i aa39 sysclk_lai differential i aa4 fbd1nbidp[0] differential i aa40 qpi2_drx_dn[10] scid diff. i aa41 vss gnd i aa42 vioc power i aa43 qpi2_dtx_dp[17] scid diff. o aa44 qpi2_dtx_dn[17] scid diff. o aa45 qpi2_dtx_dn[14] scid diff. o aa46 vss gnd i aa5 vss gnd i aa6 fbd1nbicn[12] differential i aa7 fbd1nbicp[6] differential i aa8 fbd1nbicn[6] differential i aa9 vss gnd i ab1 fbd1nbidp[12] differential i ab10 vss gnd i ab11 vss gnd i ab2 fbd1nbiclkdn0 differential i ab3 rsvd io ab36 vss gnd i ab37 qpi2_drx_dp[19] scid diff. i ab38 vss gnd i ab39 qpi2_clkrx_dp scid diff. i ab4 fbd1nbidn[0] differential i ab40 qpi2_clkrx_dn scid diff. i ab41 qpi2_drx_dp[9] scid diff. i ab42 vss gnd i ab43 qpi2_dtx_dn[19] scid diff. o table 4-2. pin list, sorted by land number (sheet 2 of 39) land # socket (emts) format io
pin listing 86 datasheet volume 1 of 2 ab44 vss gnd i ab45 qpi2_dtx_dp[13] scid diff. o ab46 qpi2_dtx_dn[13] scid diff. o ab5 fbd1nbiclkcn0 differential i ab6 fbd1nbicp[12] differential i ab7 vss gnd i ab8 fbd1nbicp[0] differential i ab9 viof power i ac1 vss gnd i ac10 viof power i ac11 viof power i ac2 fbd1nbiclkdp0 differential i ac3 fbd1nbidn[13] differential i ac36 vioc power i ac37 qpi2_drx_dn[0] scid diff. i ac38 qpi2_drx_dp[0] scid diff. i ac39 vss gnd i ac4 vss gnd i ac40 qpi2_drx_dp[8] scid diff. i ac41 qpi2_drx_dn[9] scid diff. i ac42 vioc power i ac43 qpi2_dtx_dp[19] scid diff. o ac44 qpi2_dtx_dp[12] scid diff. o ac45 qpi2_dtx_dn[12] scid diff. o ac46 qpi2_dtx_dp[11] scid diff. o ac5 fbd1nbiclkcp0 differential i ac6 fbd1nbicn[13] differential i ac7 fbd1nbicp[13] differential i ac8 fbd1nbicn[0] differential i ac9 vss gnd i ad1 fbd1nbidn[5] differential i ad10 vss gnd i ad11 vss gnd i ad2 fbd1nbidp[5] differential i ad3 fbd1nbidp[13] differential i ad36 vss gnd i ad37 rsvd io ad38 qpi2_drx_dn[1] scid diff. i ad39 qpi2_drx_dp[1] scid diff. i ad4 fbd1nbidp[1] differential i ad40 qpi2_drx_dn[8] scid diff. i table 4-2. pin list, sorted by land number (sheet 3 of 39) land # socket (emts) format io ad41 vss gnd i ad42 vioc power i ad43 qpi2_dtx_dn[10] scid diff. o ad44 qpi2_dtx_dp[10] scid diff. o ad45 vss gnd i ad46 qpi2_dtx_dn[11] scid diff. o ad5 vss gnd i ad6 fbd1nbicn[5] differential i ad7 vss gnd i ad8 fbd1nbicn[1] differential i ad9 fbd1nbicp[1] differential i ae10 vss gnd i ae11 vss gnd i ae2 fbd1nbidn[4] differential i ae3 vss gnd i ae36 vss gnd i ae37 vss gnd i ae38 rsvd io ae39 qpi2_drx_dp[7] scid diff. i ae4 fbd1nbidn[1] differential i ae40 qpi2_drx_dn[7] scid diff. i ae41 qpi2_drx_dp[6] scid diff. i ae42 vss gnd i ae43 qpi2_dtx_dn[0] scid diff. o ae44 qpi2_clktx_dn scid diff. o ae45 qpi2_clktx_dp scid diff. o ae5 fbd1nbicn[4] differential i ae6 fbd1nbicp[5] differential i ae7 vss gnd i ae8 fbd1nbicn[2] differential i ae9 viof power i af10 rsvd io af11 viof power i af2 fbd1nbidp[4] differential i af3 fbd1nbidn[3] differential i af36 vioc power i af37 qpi2_drx_dn[2] scid diff. i af38 qpi2_drx_dp[2] scid diff. i af39 vss gnd i af4 fbd1nbidp[3] differential i af40 qpi2_drx_dp[5] scid diff. i table 4-2. pin list, sorted by land number (sheet 4 of 39) land # socket (emts) format io
datasheet volume 1 of 2 87 pin listing af41 qpi2_drx_dn[6] scid diff. i af42 vioc power i af43 qpi2_dtx_dp[0] scid diff. o af44 vss gnd i af45 qpi2_dtx_dp[9] scid diff. o af5 fbd1nbicp[4] differential i af6 fbd1nbicn[3] differential i af7 fbd1nbicp[3] differential i af8 fbd1nbicp[2] differential i af9 vss gnd i ag10 rsvd io ag11 vss gnd i ag2 fbd1nbidn[2] differential i ag3 fbd1nbidp[2] differential i ag36 vss gnd i ag37 rsvd io ag38 qpi2_drx_dn[3] scid diff. i ag39 qpi2_drx_dp[3] scid diff. i ag4 vss gnd i ag40 qpi2_drx_dn[5] scid diff. i ag41 vss gnd i ag42 vioc power i ag43 qpi2_dtx_dn[8] scid diff. o ag44 qpi2_dtx_dp[8] scid diff. o ag45 qpi2_dtx_dn[9] scid diff. o ag5 rsvd io ag6 rsvd io ag7 rsvd io ag8 vss gnd i ag9 rsvd io ah10 rsvd io ah11 vss gnd i ah2 vss gnd i ah3 rsvd io ah36 vss gnd i ah37 vss gnd i ah38 rsvd io ah39 qpi2_drx_dp[4] scid diff. i ah4 rsvd io ah40 qpi2_drx_dn[4] scid diff. i ah41 qpi1_drx_dn[4] scid diff. i table 4-2. pin list, sorted by land number (sheet 5 of 39) land # socket (emts) format io ah42 vss gnd i ah43 qpi2_dtx_dn[1] scid diff. o ah44 qpi2_dtx_dn[7] scid diff. o ah45 qpi2_dtx_dp[7] scid diff. o ah5 rsvd io ah6 vss gnd i ah7 rsvd io ah8 rsvd io ah9 rsvd io aj1 vss gnd i aj10 viof power i aj11 viof power i aj2 vreg power i aj3 vss gnd i aj36 vioc power i aj37 qpi1_drx_dn[2] scid diff. i aj38 qpi1_drx_dp[2] scid diff. i aj39 vss gnd i aj4 rsvd io aj40 qpi1_drx_dn[5] scid diff. i aj41 qpi1_drx_dp[4] scid diff. i aj42 vioc power i aj43 qpi2_dtx_dp[1] scid diff. o aj44 vss gnd i aj45 qpi2_dtx_dp[6] scid diff. o aj46 rsvd io aj5 rsvd io aj6 rsvd io aj7 rsvd io aj8 rsvd io aj9 rsvd io ak1 vreg power i ak10 vss gnd i ak11 vss gnd i ak2 vreg power i ak3 vreg power i ak36 vss gnd i ak37 rsvd io ak38 qpi1_drx_dn[3] scid diff. i ak39 qpi1_drx_dp[3] scid diff. i ak4 vreg power i table 4-2. pin list, sorted by land number (sheet 6 of 39) land # socket (emts) format io
pin listing 88 datasheet volume 1 of 2 ak40 qpi1_drx_dp[5] scid diff. i ak41 vss gnd i ak42 vioc power i ak43 qpi2_dtx_dn[5] scid diff. o ak44 qpi2_dtx_dp[5] scid diff. o ak45 qpi2_dtx_dn[6] scid diff. o ak46 vss gnd i ak5 vss gnd i ak6 rsvd io ak7 vss gnd i ak8 rsvd io ak9 rsvd io al1 vreg power i al10 viof power i al11 vss gnd i al2 vreg power i al3 vreg power i al36 vss gnd i al37 vss gnd i al38 rsvd io al39 qpi1_drx_dn[6] scid diff. i al4 vreg power i al40 qpi1_drx_dp[6] scid diff. i al41 qpi1_drx_dn[7] scid diff. i al42 vss gnd i al43 qpi2_dtx_dp[2] scid diff. o al44 vss gnd i al45 qpi2_dtx_dn[4] scid diff. o al46 qpi2_dtx_dp[4] scid diff. o al5 vreg power i al6 rsvd io al7 vss gnd i al8 rsvd io al9 vss gnd i am1 fbd0sbobn[7] differential o am10 rsvd io am11 viof power i am2 vss gnd i am3 vss gnd i am36 vioc power i am37 qpi1_drx_dn[1] scid diff. i table 4-2. pin list, sorted by land number (sheet 7 of 39) land # socket (emts) format io am38 qpi1_drx_dp[1] scid diff. i am39 vss gnd i am4 fbd0sbobn[10] differential o am40 qpi1_drx_dn[8] scid diff. i am41 qpi1_drx_dp[7] scid diff. i am42 vioc power i am43 qpi2_dtx_dn[2] scid diff. o am44 qpi1_dtx_dp[3] scid diff. o am45 qpi1_dtx_dn[3] scid diff. o am46 qpi2_dtx_dp[3] scid diff. o am5 vss gnd i am6 rsvd io am7 rsvd io am8 rsvd io am9 rsvd io an1 fbd0sbobp[7] differential o an10 viof power i an11 vss gnd i an2 fbd0sbobn[6] differential o an3 vss gnd i an36 vss gnd i an37 rsvd io an38 qpi1_drx_dn[0] scid diff. i an39 qpi1_drx_dp[0] scid diff. i an4 fbd0sbobp[10] differential o an40 qpi1_drx_dp[8] scid diff. i an41 vss gnd i an42 vioc power i an43 qpi1_dtx_dn[2] scid diff. o an44 qpi1_dtx_dp[2] scid diff. o an45 vss gnd i an46 qpi2_dtx_dn[3] scid diff. o an5 fbd0sboap[7] differential o an6 fbd0sboan[7] differential o an7 vss gnd i an8 viof power i an9 vss gnd i ap1 vss gnd i ap10 te s t- h i gtl io ap11 vss gnd i ap2 fbd0sbobp[6] differential o table 4-2. pin list, sorted by land number (sheet 8 of 39) land # socket (emts) format io
datasheet volume 1 of 2 89 pin listing ap3 fbd0sbobn[8] differential o ap36 vss gnd i ap37 vss gnd i ap38 rsvd io ap39 qpi1_drx_dn[9] scid diff. i ap4 vss gnd i ap40 qpi1_drx_dp[9] scid diff. i ap41 qpi1_clkrx_dn scid diff. i ap42 vss gnd i ap43 qpi1_dtx_dp[1] scid diff. o ap44 vss gnd i ap45 qpi1_dtx_dn[4] scid diff. o ap46 qpi1_dtx_dp[4] scid diff. o ap5 vss gnd i ap6 fbd0sboap[6] differential o ap7 fbd0sboan[6] differential o ap8 fbd0sboan[8] differential o ap9 viof power i ar1 fbd0sbobp[5] differential o ar10 viof power i ar11 viof power i ar2 fbd0sbobn[5] differential o ar3 fbd0sbobp[8] differential o ar36 vioc power i ar37 qpi1_drx_dp[19] scid diff. i ar38 qpi1_drx_dn[19] scid diff. i ar39 vss gnd i ar4 fbd0sbobn[9] differential o ar40 qpi1_drx_dn[10] scid diff. i ar41 qpi1_clkrx_dp scid diff. i ar42 vioc power i ar43 qpi1_dtx_dn[1] scid diff. o ar44 qpi1_dtx_dn[5] scid diff. o ar45 qpi1_dtx_dp[5] scid diff. o ar46 qpi1_dtx_dn[6] scid diff. o ar5 vss gnd i ar6 fbd0sboan[9] differential o ar7 vss gnd i ar8 fbd0sboap[8] differential o ar9 vss gnd i at1 vss gnd i table 4-2. pin list, sorted by land number (sheet 9 of 39) land # socket (emts) format io at10 vss gnd i at11 vss gnd i at2 rsvd io at3 vss gnd i at36 vss gnd i at37 rsvd io at38 qpi1_drx_dp[18] scid diff. i at39 qpi1_drx_dn[18] scid diff. i at4 fbd0sbobp[9] differential o at40 qpi1_drx_dp[10] scid diff. i at41 vss gnd i at42 vioc power i at43 qpi1_dtx_dn[0] scid diff. o at44 qpi1_dtx_dp[0] scid diff. o at45 vss gnd i at46 qpi1_dtx_dp[6] scid diff. o at5 fbd0sboclkap0 differential o at6 fbd0sboap[9] differential o at7 fbd0sboap[5] differential o at8 fbd0sboan[5] differential o at9 viof power i au1 vss gnd i au10 vss gnd i au11 vss gnd i au2 rsvd io au3 fbd0sboclkbn0 differential o au36 vss gnd i au37 vss gnd i au38 rsvd io au39 qpi1_drx_dn[11] scid diff. i au4 fbd0sboclkbp0 differential o au40 qpi1_drx_dp[11] scid diff. i au41 qpi1_drx_dn[12] scid diff. i au42 vss gnd i au43 qpi1_dtx_dp[19] scid diff. o au44 vss gnd i au45 qpi1_dtx_dn[7] scid diff. o au46 qpi1_dtx_dp[7] scid diff. o au5 fbd0sboclkan0 differential o au6 vss gnd i au7 fbd0sboan[4] differential o table 4-2. pin list, sorted by land number (sheet 10 of 39) land # socket (emts) format io
pin listing 90 datasheet volume 1 of 2 au8 vss gnd i au9 viof power i av1 fbd0sbobn[3] differential o av10 viof power i av11 viof power i av2 fbd0sbobp[4] differential o av3 fbd0sbobn[4] differential o av36 vioc power i av37 qpi1_drx_dp[16] scid diff. i av38 qpi1_drx_dn[16] scid diff. i av39 vss gnd i av4 fbd0sbobp[0] differential o av40 qpi1_drx_dn[13] scid diff. i av41 qpi1_drx_dp[12] scid diff. i av42 vioc power i av43 qpi1_dtx_dn[19] scid diff. o av44 qpi1_dtx_dn[8] scid diff. o av45 qpi1_dtx_dp[8] scid diff. o av46 qpi1_dtx_dn[9] scid diff. o av5 vss gnd i av6 fbd0sboan[3] differential o av7 fbd0sboap[4] differential o av8 fbd0sboap[10] differential o av9 vss gnd i aw1 fbd0sbobp[3] differential o aw10 vss gnd i aw11 vss gnd i aw2 fbd0sbobn[2] differential o aw3 vss gnd i aw36 vss gnd i aw37 rsvd io aw38 qpi1_drx_dp[14] scid diff. i aw39 qpi1_drx_dn[14] scid diff. i aw4 fbd0sbobn[0] differential o aw40 qpi1_drx_dp[13] scid diff. i aw41 vss gnd i aw42 vioc power i aw43 qpi1_dtx_dp[18] scid diff. o aw44 qpi1_dtx_dn[18] scid diff. o aw45 vss gnd i aw46 qpi1_dtx_dp[9] scid diff. o table 4-2. pin list, sorted by land number (sheet 11 of 39) land # socket (emts) format io aw5 fbd0sboan[2] differential o aw6 fbd0sboap[3] differential o aw7 vss gnd i aw8 fbd0sboan[10] differential o aw9 proc_id[0] cmos o ay1 vss gnd i ay10 vss gnd i ay11 vss gnd i ay2 fbd0sbobp[2] differential o ay3 fbd0sbobn[1] differential o ay36 vss gnd i ay37 vss gnd i ay38 rsvd io ay39 qpi1_drx_dp[15] scid diff. i ay4 fbd0sbobp[1] differential o ay40 qpi1_drx_dn[15] scid diff. i ay41 qpi0_drx_dn[1] scid diff. i ay42 vss gnd i ay43 qpi1_dtx_dp[17] scid diff. o ay44 vss gnd i ay45 qpi1_clktx_dn scid diff. o ay46 qpi1_clktx_dp scid diff. o ay5 fbd0sboap[2] differential o ay6 vss gnd i ay7 fbd0sboan[1] differential o ay8 fbd0sboap[1] differential o ay9 proc_id[1] cmos o b1 vss gnd i b10 vcccore power i b11 vss gnd i b12 vcccore power i b13 vcccore power i b14 vss gnd i b15 vcccore power i b16 vcccore power i b17 vss gnd i b18 vcccore power i b19 vcccore power i b2 vss gnd i b20 vss gnd i b21 vcccore power i table 4-2. pin list, sorted by land number (sheet 12 of 39) land # socket (emts) format io
datasheet volume 1 of 2 91 pin listing b22 vcccore power i b23 vss gnd i b24 vss gnd i b25 vcccore power i b26 vcccore power i b27 vss gnd i b28 vcccore power i b29 vcccore power i b3 vss gnd i b30 vss gnd i b31 vcccore power i b32 vcccore power i b33 vss gnd i b34 vcccore power i b35 vcccore power i b36 vss gnd i b37 vcccore power i b38 vcccore power i b39 vss gnd i b4 reset_n gtl i b40 vss gnd i b41 qpi3_dtx_dp[14] scid diff. o b42 qpi3_dtx_dn[13] scid diff. o b43 qpi3_dtx_dp[11] scid diff. o b44 qpi3_dtx_dn[11] scid diff. o b45 vss gnd i b46 rsvd io b5 isense_dn gtl i b6 vss gnd i b7 vid[6] cmos io b8 vss gnd i b9 vcccore power i ba1 viof power i ba10 viof power i ba11 viof power i ba2 viof power i ba3 viof power i ba36 vioc power i ba37 qpi1_drx_dp[17] scid diff. i ba38 qpi1_drx_dn[17] scid diff. i ba39 vss gnd i table 4-2. pin list, sorted by land number (sheet 13 of 39) land # socket (emts) format io ba4 vss gnd i ba40 qpi0_drx_dn[2] scid diff. i ba41 qpi0_drx_dp[1] scid diff. i ba42 vioc power i ba43 qpi1_dtx_dn[17] scid diff. o ba44 qpi1_dtx_dn[10] scid diff. o ba45 qpi1_dtx_dp[10] scid diff. o ba46 qpi1_dtx_dn[11] scid diff. o ba5 fbd0sboan[0] differential o ba6 fbd0sboap[0] differential o ba7 viof power i ba8 viof power i ba9 vss gnd i bb10 viof power i bb11 viof power i bb2 viof power i bb3 vss gnd i bb36 vss gnd i bb37 vioc power i bb38 qpi0_drx_dn[0] scid diff. i bb39 qpi0_drx_dp[0] scid diff. i bb4 viof power i bb40 qpi0_drx_dp[2] scid diff. i bb41 vss gnd i bb42 vioc power i bb43 qpi1_dtx_dp[12] scid diff. o bb44 qpi1_dtx_dn[12] scid diff. o bb45 vss gnd i bb46 qpi1_dtx_dp[11] scid diff. o bb5 viof power i bb6 viof power i bb7 vss gnd i bb8 viof power i bb9 vss gnd i bc10 mem_throttle0_n gtl i bc11 vss gnd i bc12 vss gnd i bc13 vss gnd i bc14 vss gnd i bc15 vcache power i bc16 vss gnd i table 4-2. pin list, sorted by land number (sheet 14 of 39) land # socket (emts) format io
pin listing 92 datasheet volume 1 of 2 bc17 vcache power i bc18 vcache power i bc19 vss gnd i bc2 fbd0nbibp[11] differential i bc20 vcache power i bc21 vcache power i bc22 vss gnd i bc23 vcache power i bc24 vcache power i bc25 vss gnd i bc26 vcache power i bc27 vcache power i bc28 vss gnd i bc29 vcache power i bc3 fbd0nbibn[11] differential i bc30 vcache power i bc31 vss gnd i bc32 vcache power i bc33 vcache power i bc34 vss gnd i bc35 rsvd io bc36 qpi0_drx_dn[6] scid diff. i bc37 vss gnd i bc38 rsvd io bc39 qpi0_drx_dn[3] scid diff. i bc4 fbd0nbibn[10] differential i bc40 qpi0_drx_dp[3] scid diff. i bc41 qpi0_drx_dn[4] scid diff. i bc42 vss gnd i bc43 qpi1_dtx_dn[15] scid diff. o bc44 qpi1_dtx_dp[13] scid diff. o bc45 qpi1_dtx_dn[13] scid diff. o bc5 vss gnd i bc6 fbd0nbian[10] differential i bc7 fbd0nbiap[11] differential i bc8 fbd0nbian[11] differential i bc9 rsvd io bd10 mem_throttle1_n gtl i bd11 vss gnd i bd12 rsvd io bd13 rsvd io table 4-2. pin list, sorted by land number (sheet 15 of 39) land # socket (emts) format io bd14 vss gnd i bd15 vcache power i bd16 vss gnd i bd17 vcache power i bd18 vcache power i bd19 vss gnd i bd2 fbd0nbibn[9] differential i bd20 vcache power i bd21 vcache power i bd22 vss gnd i bd23 vcache power i bd24 vcache power i bd25 vss gnd i bd26 vcache power i bd27 vcache power i bd28 vss gnd i bd29 vcache power i bd3 vss gnd i bd30 vcache power i bd31 vss gnd i bd32 vcache power i bd33 vcache power i bd34 qpi0_drx_dn[19] scid diff. i bd35 qpi0_drx_dp[19] scid diff. i bd36 qpi0_drx_dp[6] scid diff. i bd37 qpi0_drx_dn[9] scid diff. i bd38 rsvd io bd39 vss gnd i bd4 fbd0nbibp[10] differential i bd40 qpi0_drx_dn[5] scid diff. i bd41 qpi0_drx_dp[4] scid diff. i bd42 vioc power i bd43 qpi1_dtx_dp[15] scid diff. o bd44 vss gnd i bd45 qpi1_dtx_dn[14] scid diff. o bd5 fbd0nbian[9] differential i bd6 fbd0nbiap[10] differential i bd7 vss gnd i bd8 fbd0nbiap[0] differential i bd9 rsvd io be1 vss gnd i table 4-2. pin list, sorted by land number (sheet 16 of 39) land # socket (emts) format io
datasheet volume 1 of 2 93 pin listing be10 vcc33 power i be11 vcc33 power i be12 vcc33 power i be13 vss gnd i be14 vss gnd i be15 vcache power i be16 vss gnd i be17 vcache power i be18 vcache power i be19 vss gnd i be2 fbd0nbibp[9] differential i be20 vcache power i be21 vcache power i be22 vss gnd i be23 vcache power i be24 vcache power i be25 vss gnd i be26 vcache power i be27 vcache power i be28 vss gnd i be29 vcache power i be3 fbd0nbibn[8] differential i be30 vcache power i be31 vss gnd i be32 qpi0_drx_dp[17] scid diff. i be33 qpi0_drx_dn[18] scid diff. i be34 qpi0_drx_dp[18] scid diff. i be35 qpi0_drx_dn[10] scid diff. i be36 vss gnd i be37 qpi0_drx_dp[9] scid diff. i be38 qpi0_drx_dp[8] scid diff. i be39 qpi0_drx_dn[8] scid diff. i be4 fbd0nbibp[8] differential i be40 qpi0_drx_dp[5] scid diff. i be41 vss gnd i be42 vioc power i be43 qpi1_dtx_dp[16] scid diff. o be44 qpi1_dtx_dn[16] scid diff. o be45 qpi1_dtx_dp[14] scid diff. o be46 vss gnd i be5 fbd0nbiap[9] differential i table 4-2. pin list, sorted by land number (sheet 17 of 39) land # socket (emts) format io be6 fbd0nbian[8] differential i be7 fbd0nbiap[8] differential i be8 fbd0nbian[0] differential i be9 vss gnd i bf1 fbd0nbibn[7] differential i bf10 lt-sx (test-lo) gtl i bf11 vss gnd i bf12 rsvd io bf13 vss gnd i bf14 psi_cache_n cmos o bf15 vcache power i bf16 vss gnd i bf17 vcache power i bf18 vcache power i bf19 vss gnd i bf2 fbd0nbibp[7] differential i bf20 vcache power i bf27 vcache power i bf28 vss gnd i bf29 vcache power i bf3 rsvd io bf30 vcache power i bf31 vss gnd i bf32 qpi0_drx_dn[17] scid diff. i bf33 qpi0_drx_dp[16] scid diff. i bf34 vss gnd i bf35 qpi0_drx_dp[10] scid diff. i bf36 qpi0_clkrx_dp scid diff. i bf37 qpi0_clkrx_dn scid diff. i bf38 vss gnd i bf39 qpi0_drx_dp[7] scid diff. i bf4 fbd0nbibp[0] differential i bf40 qpi0_drx_dn[7] scid diff. i bf41 vioc power i bf42 vss gnd i bf43 qpi0_dtx_dn[1] scid diff. o bf44 qpi0_dtx_dn[2] scid diff. o bf45 qpi0_dtx_dp[2] scid diff. o bf46 qpi0_dtx_dn[3] scid diff. o bf5 vss gnd i bf6 fbd0nbian[7] differential i table 4-2. pin list, sorted by land number (sheet 18 of 39) land # socket (emts) format io
pin listing 94 datasheet volume 1 of 2 bf7 vss gnd i bf8 fbd0nbian[1] differential i bf9 fbd0nbiap[1] differential i bg1 fbd0nbibn[6] differential i bg10 spdclk cmos i/od bg11 sktdis_n gtl i bg12 vss gnd i bg13 thermalert_n cmos od bg14 vss gnd i bg15 vcache power i bg16 vss gnd i bg17 vcache power i bg18 vcache power i bg19 vss gnd i bg2 rsvd io bg20 vcache power i bg27 vcache power i bg28 vss gnd i bg29 vcache power i bg3 vss gnd i bg30 vcache power i bg31 vss gnd i bg32 rsvd io bg33 qpi0_drx_dn[16] scid diff. i bg34 qpi0_drx_dp[11] scid diff. i bg35 qpi0_drx_dn[11] scid diff. i bg36 vioc power i bg37 vioc power i bg38 vioc power i bg39 vioc power i bg4 fbd0nbibn[0] differential i bg40 vss gnd i bg41 vioc power i bg42 qpi0_dtx_dn[0] scid diff. o bg43 qpi0_dtx_dp[1] scid diff. o bg44 vss gnd i bg45 rsvd io bg46 qpi0_dtx_dp[3] scid diff. o bg5 fbd0nbian[6] differential i bg6 fbd0nbiap[7] differential i bg7 vss gnd i table 4-2. pin list, sorted by land number (sheet 19 of 39) land # socket (emts) format io bg8 fbd0nbiap[2] differential i bg9 spddat cmos i/od bh1 fbd0nbibp[6] differential i bh10 bootmode[0] gtl i bh11 bootmode[1] gtl i bh12 smbdat cmos i/od bh13 vss gnd i bh14 sktid[2] cmos i bh15 rsvd io bh16 rsvd io bh17 vcache power i bh18 vcache power i bh19 vss gnd i bh2 fbd0nbibn[12] differential i bh20 vcache power i bh27 vcache power i bh28 vss gnd i bh29 vcache power i bh3 fbd0nbiclkbn0 differential i bh30 vcache power i bh31 vss gnd i bh32 qpi0_drx_dp[15] scid diff. i bh33 qpi0_drx_dn[15] scid diff. i bh34 vioc power i bh35 vioc power i bh36 vss gnd i bh37 qpi0_dtx_dp[18] scid diff. o bh38 vio_vid[1] cmos o bh39 qpi0_dtx_dn[19] scid diff. o bh4 fbd0nbiclkbp0 differential i bh40 qpi0_dtx_dp[19] scid diff. o bh41 vioc power i bh42 qpi0_dtx_dp[0] scid diff. o bh43 qpi0_dtx_dn[4] scid diff. o bh44 qpi0_dtx_dp[4] scid diff. o bh45 qpi0_dtx_dn[5] scid diff. o bh46 vss gnd i bh5 fbd0nbiap[6] differential i bh6 fbd0nbian[12] differential i bh7 fbd0nbiap[12] differential i bh8 fbd0nbian[2] differential i table 4-2. pin list, sorted by land number (sheet 20 of 39) land # socket (emts) format io
datasheet volume 1 of 2 95 pin listing bh9 vss gnd i bj1 vss gnd i bj10 runbist gtl i bj11 vss gnd i bj12 smbclk cmos i/od bj13 sktocc_n o bj14 sktid[1] cmos i bj15 flashrom_cfg[2] gtl i bj16 cvid[3] cmos o bj17 vss gnd i bj18 vcache power i bj19 vss gnd i bj2 fbd0nbibp[12] differential i bj20 vcache power i bj21 vcache power i bj22 vss gnd i bj23 vcache power i bj24 vcache power i bj25 vss gnd i bj26 vcache power i bj27 vcache power i bj28 vss gnd i bj29 vcache power i bj3 vss gnd i bj30 vcache power i bj31 vss gnd i bj32 vss gnd i bj33 qpi0_drx_dn[12] scid diff. i bj34 vss gnd i bj35 qpi0_dtx_dp[17] scid diff. o bj36 qpi0_dtx_dn[17] scid diff. o bj37 qpi0_dtx_dn[18] scid diff. o bj38 vss gnd i bj39 qpi0_dtx_dp[12] scid diff. o bj4 fbd0nbibn[5] differential i bj40 qpi0_dtx_dp[10] scid diff. o bj41 qpi0_dtx_dn[10] scid diff. o bj42 vss gnd i bj43 qpi0_dtx_dn[6] scid diff. o bj44 vss gnd i bj45 qpi0_dtx_dp[5] scid diff. o table 4-2. pin list, sorted by land number (sheet 21 of 39) land # socket (emts) format io bj46 vss gnd i bj5 vss gnd i bj6 fbd0nbibp[1] differential i bj7 vss gnd i bj8 fbd0nbiclkan0 differential i bj9 fbd0nbiclkap0 differential i bk1 vss gnd i bk10 fbd0nbiap[5] differential i bk11 flashrom_wp_n gtl od bk12 sm_wp cmos i bk13 flashrom_cs_n[0] gtl od bk14 sktid[0] cmos i bk15 vss gnd i bk16 cvid[2] cmos o bk17 vsscachesense power io bk18 vcachesense power io bk19 vss gnd i bk2 fbd0nbibn[13] differential i bk20 vcache power i bk21 vcache power i bk22 vss gnd i bk23 vcache power i bk24 vcache power i bk25 vss gnd i bk26 vcache power i bk27 vcache power i bk28 vss gnd i bk29 vcache power i bk3 fbd0nbibp[13] differential i bk30 vcache power i bk31 vss gnd i bk32 qpi0_drx_dp[14] scid diff. i bk33 qpi0_drx_dp[12] scid diff. i bk34 vioc power i bk35 qpi0_dtx_dp[16] scid diff. o bk36 qpi0_dtx_dp[14] scid diff. o bk37 qpi0_dtx_dn[14] scid diff. o bk38 vio_vid[2] cmos o bk39 qpi0_dtx_dn[12] scid diff. o bk4 fbd0nbibp[5] differential i bk40 vss gnd i table 4-2. pin list, sorted by land number (sheet 22 of 39) land # socket (emts) format io
pin listing 96 datasheet volume 1 of 2 bk41 qpi0_dtx_dp[8] scid diff. o bk42 qpi0_dtx_dn[8] scid diff. o bk43 qpi0_dtx_dp[6] scid diff. o bk44 qpi0_dtx_dp[7] scid diff. o bk45 qpi0_dtx_dn[7] scid diff. o bk46 vss gnd i bk5 fbd0nbibn[4] differential i bk6 fbd0nbibn[1] differential i bk7 vss gnd i bk8 fbd0nbian[13] differential i bk9 fbd0nbian[5] differential i bl1 vss gnd i bl10 fbd0nbian[3] differential i bl11 flashrom_clk gtl od bl12 flashrom_dati gtl i bl13 vss gnd i bl14 flashrom_cs_n[2] gtl od bl15 flashrom_cfg[0] gtl i bl16 cvid[1] cmos o bl17 cvid[5] cmos o bl18 cvid[7] cmos o bl19 vss gnd i bl2 vss gnd i bl20 vcache power i bl21 vcache power i bl22 vss gnd i bl23 vcache power i bl24 vcache power i bl25 vss gnd i bl26 vcache power i bl27 vcache power i bl28 vss gnd i bl29 vcache power i bl3 vss gnd i bl30 vcache power i bl31 vss gnd i bl32 qpi0_drx_dn[14] scid diff. i bl33 vss gnd i bl34 vioc power i bl35 qpi0_dtx_dn[16] scid diff. o bl36 vss gnd i table 4-2. pin list, sorted by land number (sheet 23 of 39) land # socket (emts) format io bl37 qpi0_dtx_dn[13] scid diff. o bl38 vss gnd i bl39 qpi0_dtx_dp[11] scid diff. o bl4 vss gnd i bl40 qpi0_dtx_dn[11] scid diff. o bl41 qpi0_clktx_dn scid diff. o bl42 qpi0_dtx_dp[9] scid diff. o bl43 qpi0_dtx_dn[9] scid diff. o bl44 vss gnd i bl45 vss gnd i bl46 vss gnd i bl5 fbd0nbibp[4] differential i bl6 fbd0nbibn[2] differential i bl7 fbd0nbibp[2] differential i bl8 fbd0nbiap[13] differential i bl9 vss gnd i bm1 test[3] gnd io bm10 fbd0nbiap[3] differential i bm11 vss gnd i bm12 flashrom_dato gtl od bm13 flashrom_cs_n[1] gtl od bm14 flashrom_cs_n[3] gtl od bm15 flashrom_cfg[1] gtl i bm16 vss gnd i bm17 cvid[4] cmos o bm18 cvid[6] cmos o bm19 vss gnd i bm2 vss gnd i bm20 vcache power i bm21 vcache power i bm26 vcache power i bm27 vcache power i bm28 vss gnd i bm29 vcache power i bm3 vss gnd i bm30 vcache power i bm31 vss gnd i bm32 qpi0_drx_dp[13] scid diff. i bm33 qpi0_drx_dn[13] scid diff. i bm34 vss gnd i bm35 qpi0_dtx_dp[15] scid diff. o table 4-2. pin list, sorted by land number (sheet 24 of 39) land # socket (emts) format io
datasheet volume 1 of 2 97 pin listing bm36 qpi0_dtx_dn[15] scid diff. o bm37 qpi0_dtx_dp[13] scid diff. o bm38 vio_vid[3] cmos o bm39 vio_vid[4] cmos o bm4 vss gnd i bm40 vss gnd i bm41 qpi0_clktx_dp scid diff. o bm42 vss gnd i bm43 vss gnd i bm44 vss gnd i bm45 vss gnd i bm46 test[2] gnd i bm5 fbd0nbibn[3] differential i bm6 fbd0nbibp[3] differential i bm7 vss gnd i bm8 fbd0nbian[4] differential i bm9 fbd0nbiap[4] differential i c1 vss gnd i c10 vcccore power i c11 vss gnd i c12 vcccore power i c13 vcccore power i c14 vss gnd i c15 vcccore power i c16 vcccore power i c17 vss gnd i c18 vcccore power i c19 vcccore power i c2 vss gnd i c20 vss gnd i c21 vcccore power i c22 vcccore power i c23 vss gnd i c24 vss gnd i c25 vcccore power i c26 vcccore power i c27 vss gnd i c28 vcccore power i c29 vcccore power i c3 prdy_n cmos o c30 vss gnd i table 4-2. pin list, sorted by land number (sheet 25 of 39) land # socket (emts) format io c31 vcccore power i c32 vcccore power i c33 vss gnd i c34 vcccore power i c35 vcccore power i c36 vss gnd i c37 vcccore power i c38 vcccore power i c39 qpi3_dtx_dn[16] scid diff. o c4 force_pr_n gtl i c40 qpi3_dtx_dp[16] scid diff. o c41 vss gnd i c42 qpi3_dtx_dp[13] scid diff. o c43 vss gnd i c44 qpi3_dtx_dp[10] scid diff. o c45 qpi3_dtx_dn[10] scid diff. o c46 rsvd io c5 vss gnd i c6 vid[5] cmos io c7 vid[4] cmos io c8 vss gnd i c9 vcccore power i d1 vss gnd i d10 vcccore power i d11 vss gnd i d12 vcccore power i d13 vcccore power i d14 vss gnd i d15 vcccore power i d16 vcccore power i d17 vss gnd i d18 vcccore power i d19 vcccore power i d2 prochot_n gtl od d20 vss gnd i d21 vcccore power i d22 vcccore power i d23 vss gnd i d24 vss gnd i d25 vcccore power i d26 vcccore power i table 4-2. pin list, sorted by land number (sheet 26 of 39) land # socket (emts) format io
pin listing 98 datasheet volume 1 of 2 d27 vss gnd i d28 vcccore power i d29 vcccore power i d3 preq_n cmos i d30 vss gnd i d31 vcccore power i d32 vcccore power i d33 vss gnd i d34 vcccore power i d35 vcccore power i d36 vss gnd i d37 vcccore power i d38 vcccore power i d39 vss gnd i d4 rsvd io d40 qpi3_dtx_dp[19] scid diff. o d41 qpi3_dtx_dp[15] scid diff. o d42 qpi3_dtx_dn[15] scid diff. o d43 peci cmos io d44 qpi3_clktx_dp scid diff. o d45 vss gnd i d46 vss gnd i d5 nmi gtl i d6 vid[3] cmos io d7 vid[2] cmos io d8 vss gnd i d9 vcccore power i e1 mbp[6]_n gtl io e10 vcccore power i e11 vss gnd i e12 vcccore power i e13 vcccore power i e14 vss gnd i e15 vcccore power i e16 vcccore power i e17 vss gnd i e18 vcccore power i e19 vcccore power i e2 mbp[3]_n gtl io e20 vss gnd i e27 vss gnd i table 4-2. pin list, sorted by land number (sheet 27 of 39) land # socket (emts) format io e28 vcccore power i e29 vcccore power i e3 mbp[5]_n gtl io e30 vss gnd i e31 vcccore power i e32 vcccore power i e33 vss gnd i e34 vcccore power i e35 vcccore power i e36 vss gnd i e37 vcccore power i e38 vcccore power i e39 qpi3_dtx_dn[18] scid diff. o e4 mbp[7]_n gtl io e40 qpi3_dtx_dn[19] scid diff. o e41 vss gnd i e42 qpi3_dtx_dp[12] scid diff. o e43 vss gnd i e44 qpi3_clktx_dn scid diff. o e45 qpi3_dtx_dn[9] scid diff. o e46 qpi3_dtx_dp[9] scid diff. o e5 vss gnd i e6 vid[1] cmos io e7 vid[0] cmos io e8 vss gnd i e9 vcccore power i f1 mbp[2]_n gtl io f10 vcccore power i f11 vss gnd i f12 vcccore power i f13 vcccore power i f14 vss gnd i f15 vcccore power i f16 vcccore power i f17 vss gnd i f18 vcccore power i f19 vcccore power i f2 mbp[1]_n gtl io f20 vss gnd i f27 vss gnd i f28 vcccore power i table 4-2. pin list, sorted by land number (sheet 28 of 39) land # socket (emts) format io
datasheet volume 1 of 2 99 pin listing f29 vcccore power i f3 vss gnd i f30 vss gnd i f31 vcccore power i f32 vcccore power i f33 vss gnd i f34 vcccore power i f35 vcccore power i f36 vss gnd i f37 vcccore power i f38 vcccore power i f39 qpi3_dtx_dp[18] scid diff. o f4 mbp[4]_n gtl io f40 qpi3_dtx_dp[17] scid diff. o f41 qpi3_dtx_dn[17] scid diff. o f42 qpi3_dtx_dn[12] scid diff. o f43 qpi3_dtx_dn[4] scid diff. o f44 qpi3_dtx_dp[4] scid diff. o f45 vss gnd i f46 qpi3_dtx_dp[8] scid diff. o f5 thermtrip_n gtl-od o f6 vsscoresense power io f7 vcoresense power io f8 vss gnd i f9 vcccore power i g1 vss gnd i g10 vcccore power i g11 vss gnd i g12 vcccore power i g13 vcccore power i g14 vss gnd i g15 vcccore power i g16 vcccore power i g17 vss gnd i g18 vcccore power i g19 vcccore power i g2 mbp[0]_n gtl io g20 vss gnd i g27 vss gnd i g28 vcccore power i g29 vcccore power i table 4-2. pin list, sorted by land number (sheet 29 of 39) land # socket (emts) format io g3 error0_n gtl od io g30 vss gnd i g31 vcccore power i g32 vcccore power i g33 vss gnd i g34 vcccore power i g35 vcccore power i g36 vss gnd i g37 vcccore power i g38 vcccore power i g39 vss gnd i g4 error1_n gtl-od io g40 vss gnd i g41 pwrgood cmos i g42 vss gnd i g43 qpi3_dtx_dn[2] scid diff. o g44 qpi3_dtx_dn[7] scid diff. o g45 qpi3_dtx_dp[7] scid diff. o g46 qpi3_dtx_dn[8] scid diff. o g5 vss gnd i g6 rsvd io g7 psi_n cmos o g8 vss gnd i g9 vcccore power i h1 fbd1sbodp[5] differential o h10 vcccore power i h11 vss gnd i h12 vcccore power i h13 vcccore power i h14 vss gnd i h15 vcccore power i h16 vcccore power i h17 vss gnd i h18 vcccore power i h19 vcccore power i h2 fbd1sbodn[5] differential o h20 vss gnd i h21 vcccore power i h22 vcccore power i h23 vss gnd i h24 vss gnd i table 4-2. pin list, sorted by land number (sheet 30 of 39) land # socket (emts) format io
pin listing 100 datasheet volume 1 of 2 h25 vcccore power i h26 vcccore power i h27 vss gnd i h28 vcccore power i h29 vcccore power i h3 fbd1sbodn[9] differential o h30 vss gnd i h31 vcccore power i h32 vcccore power i h33 vss gnd i h34 vcccore power i h35 vcccore power i h36 vss gnd i h37 vcccore power i h38 vcccore power i h39 vss gnd i h4 vss gnd i h40 vss gnd i h41 viopwrgood cmos i h42 qpi3_dtx_dn[1] scid diff. o h43 qpi3_dtx_dp[2] scid diff. o h44 vss gnd i h45 qpi3_dtx_dp[6] scid diff. o h46 vss gnd i h5 fbd1sbocn[9] differential o h6 fbd1sbocp[5] differential o h7 fbd1sbocn[5] differential o h8 vss gnd i h9 rsvd io j1 fbd1sboclkdp0 differential o j10 vcccore power i j11 vss gnd i j12 vcccore power i j13 vcccore power i j14 vss gnd i j15 vcccore power i j16 vcccore power i j17 vss gnd i j18 vcccore power i j19 vcccore power i j2 vss gnd i table 4-2. pin list, sorted by land number (sheet 31 of 39) land # socket (emts) format io j20 vss gnd i j21 vcccore power i j22 vcccore power i j23 vss gnd i j24 vss gnd i j25 vcccore power i j26 vcccore power i j27 vss gnd i j28 vcccore power i j29 vcccore power i j3 fbd1sbodp[9] differential o j30 vss gnd i j31 vcccore power i j32 vcccore power i j33 vss gnd i j34 vcccore power i j35 vcccore power i j36 vss gnd i j37 vcccore power i j38 vcccore power i j39 vss gnd i j4 fbd1sbodn[6] differential o j40 qpi3_dtx_dn[0] scid diff. o j41 qpi3_dtx_dp[0] scid diff. o j42 qpi3_dtx_dp[1] scid diff. o j43 qpi3_dtx_dn[3] scid diff. o j44 qpi3_dtx_dp[3] scid diff. o j45 qpi3_dtx_dn[6] scid diff. o j46 qpi3_dtx_dp[5] scid diff. o j5 fbd1sbocp[9] differential o j6 fbd1sboclkcp0 differential o j7 vss gnd i j8 fbd1sbocn[6] differential o j9 rsvd io k1 fbd1sboclkdn0 differential o k10 tclk gtl i k11 vss gnd i k12 vcccore power i k13 vcccore power i k14 vss gnd i k15 vcccore power i table 4-2. pin list, sorted by land number (sheet 32 of 39) land # socket (emts) format io
datasheet volume 1 of 2 101 pin listing k16 vcccore power i k17 vss gnd i k18 vcccore power i k19 vcccore power i k2 fbd1sbodn[4] differential o k20 vss gnd i k21 vcccore power i k22 vcccore power i k23 vss gnd i k24 vss gnd i k25 vcccore power i k26 vcccore power i k27 vss gnd i k28 vcccore power i k29 vcccore power i k3 fbd1sbodp[4] differential o k30 vss gnd i k31 vcccore power i k32 vcccore power i k33 vss gnd i k34 vcccore power i k35 vcccore power i k36 vss gnd i k37 vcccore power i k38 vcccore power i k39 vss gnd i k4 fbd1sbodp[6] differential o k40 vss gnd i k41 vss gnd i k42 vss gnd i k43 vss gnd i k44 vss gnd i k45 vss gnd i k46 qpi3_dtx_dn[5] scid diff. o k5 vss gnd i k6 fbd1sboclkcn0 differential o k7 vss gnd i k8 fbd1sbocp[6] differential o k9 vss gnd i l1 fbd1sbodn[3] differential o l10 tdo gtl od o table 4-2. pin list, sorted by land number (sheet 33 of 39) land # socket (emts) format io l11 vss gnd i l2 fbd1sbodp[3] differential o l3 vss gnd i l36 vss gnd i l37 vss gnd i l38 qpi3_drx_dp[16] scid diff. i l39 qpi3_drx_dp[15] scid diff. i l4 vss gnd i l40 qpi3_drx_dn[15] scid diff. i l41 qpi3_drx_dp[13] scid diff. i l42 qpi3_drx_dp[12] scid diff. i l43 qpi3_drx_dn[12] scid diff. i l44 qpi3_drx_dn[11] scid diff. i l45 vss gnd i l46 vss gnd i l5 fbd1sbocn[3] differential o l6 vss gnd i l7 fbd1sbocp[4] differential o l8 fbd1sbocn[4] differential o l9 tdi gtl i m1 vss gnd i m10 trst_n gtl i m11 vss gnd i m2 vss gnd i m3 fbd1sbodp[7] differential o m36 vioc power i m37 vss gnd i m38 qpi3_drx_dn[16] scid diff. i m39 rsvd io m4 fbd1sbodn[7] differential o m40 qpi3_drx_dp[14] scid diff. i m41 qpi3_drx_dn[13] scid diff. i m42 vss gnd i m43 qpi3_drx_dp[10] scid diff. i m44 qpi3_drx_dp[11] scid diff. i m45 qpi3_clkrx_dp scid diff. i m46 vss gnd i m5 fbd1sbocp[3] differential o m6 fbd1sbocn[2] differential o m7 fbd1sbocp[2] differential o m8 vss gnd i table 4-2. pin list, sorted by land number (sheet 34 of 39) land # socket (emts) format io
pin listing 102 datasheet volume 1 of 2 m9 tms gtl i n1 fbd1sbodn[1] differential o n10 vss gnd i n11 vss gnd i n2 fbd1sbodp[2] differential o n3 fbd1sbodn[2] differential o n36 vss gnd i n37 qpi3_drx_dp[17] scid diff. i n38 qpi3_drx_dn[17] scid diff. i n39 vss gnd i n4 fbd1sbodp[8] differential o n40 qpi3_drx_dn[14] scid diff. i n41 qpi3_drx_dn[1] scid diff. i n42 qpi3_drx_dp[1] scid diff. i n43 qpi3_drx_dn[10] scid diff. i n44 vss gnd i n45 qpi3_clkrx_dn scid diff. i n46 qpi3_drx_dp[9] scid diff. i n5 vss gnd i n6 fbd1sbocn[1] differential o n7 fbd1sbocp[7] differential o n8 fbd1sbocn[7] differential o n9 vss gnd i p1 fbd1sbodp[1] differential o p10 viof power i p11 viof power i p2 fbd1sbodn[0] differential o p3 vss gnd i p36 vioc power i p37 rsvd io p38 rsvd io p39 qpi3_drx_dp[18] scid diff. i p4 fbd1sbodn[8] differential o p40 qpi3_drx_dn[18] scid diff. i p41 qpi3_drx_dn[0] scid diff. i p42 vss gnd i p43 vss gnd i p44 qpi3_drx_dn[8] scid diff. i p45 qpi3_drx_dp[8] scid diff. i p46 qpi3_drx_dn[9] scid diff. i p5 fbd1sbocn[0] differential o table 4-2. pin list, sorted by land number (sheet 35 of 39) land # socket (emts) format io p6 fbd1sbocp[1] differential o p7 vss gnd i p8 fbd1sbocp[10] differential o p9 rsvd io r1 vss gnd i r10 viof power i r11 viof power i r2 fbd1sbodp[0] differential o r3 fbd1sbodp[10] differential o r36 vss gnd i r37 vss gnd i r38 qpi3_drx_dp[19] scid diff. i r39 qpi3_drx_dn[19] scid diff. i r4 fbd1sbodn[10] differential o r40 vss gnd i r41 qpi3_drx_dp[0] scid diff. i r42 qpi3_drx_dp[2] scid diff. i r43 qpi3_drx_dn[5] scid diff. i r44 qpi3_drx_dp[5] scid diff. i r45 qpi3_drx_dp[7] scid diff. i r46 vss gnd i r5 fbd1sbocp[0] differential o r6 fbd1sbocp[8] differential o r7 fbd1sbocn[8] differential o r8 fbd1sbocn[10] differential o r9 rsvd io t1 viof power i t10 vss gnd i t11 vss gnd i t2 viof power i t3 vss gnd i t36 vss gnd i t37 vss gnd i t38 sysclk_dn differential i t39 qpi2_drx_dp[15] scid diff. i t4 viof power i t40 qpi2_drx_dn[15] scid diff. i t41 qpi2_drx_dp[14] scid diff. i t42 qpi3_drx_dn[2] scid diff. i t43 qpi3_drx_dp[3] scid diff. i t44 vss gnd i table 4-2. pin list, sorted by land number (sheet 36 of 39) land # socket (emts) format io
datasheet volume 1 of 2 103 pin listing t45 qpi3_drx_dn[7] scid diff. i t46 qpi3_drx_dp[6] scid diff. i t5 vss gnd i t6 viof power i t7 viof power i t8 viof power i t9 vss gnd i u1 viof power i u10 viof power i u11 viof power i u2 vss gnd i u3 fbd1nbidp[10] differential i u36 vioc power i u37 qpi2_drx_dp[17] scid diff. i u38 sysclk_dp differential i u39 vss gnd i u4 fbd1nbidn[10] differential i u40 qpi2_drx_dp[13] scid diff. i u41 qpi2_drx_dn[14] scid diff. i u42 vss gnd i u43 qpi3_drx_dn[3] scid diff. i u44 qpi3_drx_dn[4] scid diff. i u45 qpi3_drx_dp[4] scid diff. i u46 qpi3_drx_dn[6] scid diff. i u5 viof power i u6 fbd1nbicn[9] differential i u7 vss gnd i u8 viof power i u9 viof power i v1 fbd1nbidn[8] differential i v10 vss gnd i v11 vss gnd i v2 fbd1nbidp[9] differential i v3 fbd1nbidn[9] differential i v36 vss gnd i v37 qpi2_drx_dn[17] scid diff. i v38 qpi2_drx_dp[16] scid diff. i v39 qpi2_drx_dn[16] scid diff. i v4 fbd1nbidp[11] differential i v40 qpi2_drx_dn[13] scid diff. i v41 vss gnd i table 4-2. pin list, sorted by land number (sheet 37 of 39) land # socket (emts) format io v42 vioc power i v43 vioc power i v44 vioc power i v45 vioc power i v46 vss gnd i v5 vss gnd i v6 fbd1nbicp[9] differential i v7 fbd1nbicp[10] differential i v8 fbd1nbicn[10] differential i v9 vss gnd i w1 fbd1nbidp[8] differential i w10 vss gnd i w11 vss gnd i w2 fbd1nbidn[7] differential i w3 vss gnd i w36 vss gnd i w37 vss gnd i w38 rsvd io w39 qpi2_drx_dp[12] scid diff. i w4 fbd1nbidn[11] differential i w40 qpi2_drx_dn[12] scid diff. i w41 qpi2_drx_dp[11] scid diff. i w42 vss gnd i w43 qpi2_dtx_dn[18] scid diff. o w44 qpi2_dtx_dp[16] scid diff. o w45 qpi2_dtx_dn[16] scid diff. o w46 qpi2_dtx_dp[15] scid diff. o w5 fbd1nbicn[7] differential i w6 vss gnd i w7 vss gnd i w8 fbd1nbicp[11] differential i w9 rsvd io y1 vss gnd i y10 rsvd io y11 viof power i y2 fbd1nbidp[7] differential i y3 fbd1nbidn[6] differential i y36 vioc power i y37 qpi2_drx_dp[18] scid diff. i y38 qpi2_drx_dn[18] scid diff. i y39 vss gnd i table 4-2. pin list, sorted by land number (sheet 38 of 39) land # socket (emts) format io
pin listing 104 datasheet volume 1 of 2 y4 fbd1nbidp[6] differential i y40 qpi2_drx_dp[10] scid diff. i y41 qpi2_drx_dn[11] scid diff. i y42 vioc power i y43 qpi2_dtx_dp[18] scid diff. o y44 vss gnd i y45 qpi2_dtx_dp[14] scid diff. o y46 qpi2_dtx_dn[15] scid diff. o y5 fbd1nbicp[7] differential i y6 fbd1nbicp[8] differential i y7 fbd1nbicn[8] differential i y8 fbd1nbicn[11] differential i y9 rsvd io table 4-2. pin list, sorted by land number (sheet 39 of 39) land # socket (emts) format io
datasheet volume 1 of 2 105 signal definitions 5 signal definitions table 5-1. signal definitions (sheet 1 of 6) name type description bootmode[1:0] i the bootmode[1:0] inputs are to specify which mode the intel xeon processor e7- 8800/4800/2800 product families processor will boot to. for details on the modes refer to the intel? xeon? processor 7500 series datasheet, volume 2 . cvid[7:1] o voltage id driven ou t to the vr 11.1 for dynamic/static adjustment of processor voltage set point. see vcache below. this signal has on die termination. error[0]_n io pulsed signal. as output, signals un-corrected error condition of the processor. as an input, can be programmed to signal smi to the cores. open drain error[1]_n io level signal. as output, signals fatal error condition of the processor. as an input, can be programmed to signal smi to the cores. open drain. fbd0nbi[a/b][p/n][13:0] i these differential pair data signals generated from the branch zero, channel a and b of intel? smi links are input to the intel xeon processor e7-8800/4800/2800 product familie s processor. example: fbd0nbiap[0] intel smi branch 0, north bound data input lane 0 signal of channel a and positive bit of the differential pair. fbd0nbiclk[a/b][p/n]0 i these different ial pair clock signals generated from the branch zero, channel a and b of intel? smi links are input to the intel xeon processor e7-8800/4800/2800 product familie s processor. example: fbd0nbiclkap0 intel smi branch 0, northbound clock input signal of channel a and positive bit of the differential pair. fbd0sbo[a/b][p/n][10:0] o these differential pair output data signals generated from intel xeon processor e7- 8800/4800/2800 product families processor to the branch zero, channel a and b of intel? smi links. example: fbd0sboap[0] intel smi branch 1, southbound data output lane 0 signal of channel a and positive bit of the differential pair. intel smi 0nbia/bp/n[13:0] interface name branch number north bound input channel differential pair polarity positive/ negative lane number intel smi 0nbiclka/bp/n interface name branch number north bound input clock channel differential pair polarity positive/ negative intel smi 0sboa/bp/n[10:0] interface name branch number south bound output channel differential pair polarity positive/ negative lane number
signal definitions 106 datasheet volume 1 of 2 fbd0sboclk[a/b][p/n]0 o these differential pair output clock signals generated from intel xeon processor e7- 8800/4800/2800 product families processor are in puts to the branch zero, channel a and b of intel? smi links. example: fbd0sbiclkap0 intel smi branch 0, south bound clock output signal of channel a and positive bit of the differential pair. fbd1nbi[c/d][p/n][13:0] i these differential pair output data signals generated from intel xeon processor e7- 8800/4800/2800 product families processor are inputs to the branch one, channel c and d of intel? smi links. example: fbd1nbiap[0] intel smi branch 1, north bound data input lane 0 signal of channel a and positive bit of the differential pair. fbd1nbiclk[c/d][p/n]0 i these differential pair clock si gnals generated from the branch one, channel c and d of intel? smi links are input to the intel xeon processor e7-8800/4800/2800 product families processor. example: fbd1nbiclkap0 intel smi branch 1, northbound clock input signal of channel a and positive bit of the differential pair. fbd1sbo[c/d][p/n][10:0] o these differential pair output data signals generated from intel xeon processor e7- 8800/4800/2800 product families processor to the branch one, channel c and d of intel? smi links. example: fbd1sboap[0] intel smi branch 1, south bound data output lane 0 signal of channel a and positive bit of the differential pair. table 5-1. signal definitions (sheet 2 of 6) name type description intel smi 0sboclka/bp/n interface name branch number south bound output clock channel differential pair polarity positive/ negative intel smi 1nbic/dp/n[13:0] interface name branch number north bound input channe l differential pair polarity positive/ negative lane number intel smi 1nbiclkc/dp/n interface name branch number north bound input clock channe l differential pair polarity positive/ negative intel smi 1 nb o c/d p/n [10:0] interface name branch number north bound output channel differential pair polarity positive/ negative lane number
datasheet volume 1 of 2 107 signal definitions fbd1sboclk[c/d][p/n]0 o these differential pair output clock signals generated from intel xeon processor e7- 8800/4800/2800 product families processor ar e inputs to the branch one, channel c and d of intel? smi links. example: fbd1sbiclkap0 intel smi branch 1, south bound clock output signal of channel a and positive bit of the differential pair. flashrom_cfg[2:0] i these are in put signals to the intel xeon processor e7-8800/4800/2800 product families processor that would initialize and map the serial flash rom upon reset. after the reset is deasserted this input would be ignored by the processor logic. flashrom_clk o serial flash rom clock. flashrom_cs[3:0]_n o serial flash rom chip selects. up to four separate flash rom parts may be used. flashrom_dati i serial data input (from rom(s) to processor). flashrom_dato o serial data output (from processor to rom(s)). flashrom_wp_n o flash rom write-protect. force_pr_n i force processor power reduction by activation of a tcc. isense_d[n/p] io current sense for vcore vr11.1 lt-sx (test-lo) i in platforms supporting the intel txt feature, the intel txt pin on the processor should be variable setting and driven based on the processor type installed. with intel xeon processor e7-8800/4800/2800 product families processor installed, the intel txt pin should be driven high to support intel txt. with intel? xeon? processor 7500 series installed the intel txt pin should be driven low. note that txt is not supported on the intel? xeon? processor 7500 series. on platforms not supporting the txt feature, the pin can be strapped low. for intel? xeon? processor 7500 series debug purposes, you will need that ability to pull intel txt low. mbp[7:0] io sideband signals connecting to xdp header for run-time control and debug. mem_throttle[1:0]_n i when asserted, the internal me mory controllers throttle the memory command issue rate to a configurable fraction of the nominal command rate settings. mem_throttle[1] corresponds to me m_ctrl behind the ha xxx 11, and mem_throttle[0] corresponds to mem_ctrl behind ha xxx 01. nmi i interrupt input. active high. must be minimum of three clocks. peci io processor sideband access via peci interface. prdy_n o processor debug interface. preq_n i processor debug interface. proc_id[1:0] o processor id. 11: intel? xeon? processor 7500. 10: intel xeon processor e7-8800/ 4800/2800 product families. 01, 00: reserved for future generations. prochot_n o the assertion of prochot_n (processor hot) indicates that the processor die temperature has reached its thermal limit. open drain output. psi_cache_n o vcache power status indicator signal to the vr that the processor is in package c3 or c6 power states so the vr can use fewer phases. this signal has on die termination of 50 ohms. psi_n o vcore power status indicator signal to th e vr that the processor is in package c3 or c6 power states so the vr can use fewer phases. this signal has on die termination of 50 ohms. table 5-1. signal definitions (sheet 3 of 6) name type description intel smi 1sboclkc/dp/n interface name branch number south bound output clock channel differential pair polarity positive/ negative
signal definitions 108 datasheet volume 1 of 2 pwrgood i the processor requires this signal to be a clean indication that all intel xeon processor e7-8800/4800/2800 product families processor clocks and power supplies are stable and within their specifications. ?clean? implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specificati on. the signal must then transition monotonically to a high state. pwrgoodcan be driven inactive at any time, but clocks and power must again be st able before a subsequent rising edge of pwrgood. the pwrgood signal must be supplied to the processor at 1.1v. this signal is used to protect internal circuits against voltag e sequencing issues. it should be driven high throughout boundary scan operation. vccstby33 signal should be stable for 10 sysclocks before pwrgood is asserted. qpi[3:0]_drx_d[p/n][19:0], qpi[3:0]_clkrx_d[p/n] i these intel qpi input data signals prov ide means of communication between two intel qpi ports via one uni-directional tran sfer link (in). the rx links, are terminally ground referenced. these signals can be configured as a full width link with 20 active lanes, a half width link with 10 active lanes or as a quarter width link with five active lanes. example: qpi4rpdat[0] represents intel qpi port 5 data, lane 0,receive signal and positive bit of the differential pair. qpi[3:0]_dtx_d[p/ n][19:0],qpi[3:0]_clktx_d[p/n] o these intel qpi output data signals provide means of communication between two intel qpi ports via one uni-directional transf er link (out).the links , tx, are terminally ground referenced. these signals can be configured as a full width link with 20 active lanes, a half width link with 10 active lanes or as a quarter width link with five active lanes. example: qpi4rpdat[0] represents intel qpi port 5 data, lane 0,transmit signal and positive bit of the differential pair. reset_n i asserting the reset_n signal resets th e processor to a known state and invalidates its internal caches without writing back any of their contents. bootmode[0:1] signals are sampled at the active-to-inactive transition of reset_n for selecting appropriate bootmode. also runbist is sampled at the active-to-inactive transition of reset_n to select bist operation. rsvd these pins are reserved and should be treated as no connect, left unconnected. runbist i this input pin is sample d on a active-to-inactive transition of reset_n. if sampled high, this enables bist (recommended). sktdis_n i sampled with the rising edge of reset_n input. asserted, signal will disable the socket, tri-state i/o. sktid[2:0] i socket id strapping pins. these pins determine the addresses to be used on the smbus to access the processor. sktocc_n o static signal, asserted low when the socket is occupied with processor. sm_wp i wp (write protect) can be used to write protect the scratch eeprom. the scratch eeprom is write-protecte d when this input is pulled high to vccstby33. table 5-1. signal definitions (sheet 4 of 6) name type description intel qpi interface 3:0 r p/n dat[19:0] interface name port number receiver differential pair polarity positive/ negative lane number intel qpi interface 3:0 t p/n dat[19:0] interface name port number transmitter differential pair polarity positive/ negative lane number
datasheet volume 1 of 2 109 signal definitions smbclk i/o the smbus clock (smbclk) signal is an input clock to the system management logic which is required for operation of the system management features of the intel xeon processor e7-8800/4800/2800 product families processor. this clock is driven by the smbus controller and is asynchronous to other clocks in the processor. this is an open drain signal. smbdat i/o the smbus data (smbdat) signal is the data signal for the smbus. this signal provides the single-bit mechanism for transferring data between smbus devices. this is an open drain signal. spdclk i/o this is a bi-directional clock signal between intel xeon processor e7-8800/4800/ 2800 product families processor, dram spd registers and external components on the board. this is an open drain signal. spddat i/o this is a bi-directional data sign al between intel xeon processor e7-8800/4800/2800 product families proc essor, dram spd registers an d external components on the board. this is an open drain signal. sysclk_dp/sysclk_dp i the differential clock pair sysclk_dp/sysclk_dn provides the fundamental clock source for the intel xeon processor e7-8800/4800/2800 product families processor. all processor link agents must receive thes e signals to drive their outputs and latch their inputs. all external timing parameters are specified with respect to the rising edge of sysclk crossing the falling edge of sysclk_n. these differential clock pair should not be asserted until vcccore, vioc, viof, vcache and vcc33 are stabilized. sysclk_lai/sysclk_lai_n i these are reference clocks used only for debug purposes. electrical specifications on these clocks are identical to sysclk_dp/sysclk_dn. tck i test clock (tck) provides the clock input for the processor tap. tdi i test data in (tdi) transfers serial test data into the processor. tdi provides the serial input needed for jt ag specification support. tdo o test data out (tdo) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specificati on support. this is an open drain output. test[3:0] i four corner pins used to study socket corner join t reliability. vss on package, however, not required to be connected. test-hi i strap pins to vio via tbd resistor. thermalert_n o thermal alert (thermalert_n) is an output signal and is asserted when the on-die thermal sensors readings exceed a pre-programmed threshold. thermtrip_n o the processor protects itself from catastrophic overheating by use of an internal thermal sensor. to ensure that there are no false trips, thermal trip (thermtrip_n) will activate at a temperature that is ab out 115c as measured at the core. once activated, the processor will stop all ex ecution and the signal remains latched until reset_n goes active. it is strongly reco mmended that all power be removed from the processor before bringing the processor back up. if the temperature has not dropped below the trip level, the processo r will continue to drive thermtrip_n and remain stopped. strapping is 1k-10k ohms. tms i test mode select (tms) is a jtag specif ication support signal used by debug tools. trst_n i test reset (trst_n) resets the tap logi c. trst_n must be dr iven electrically low during power on reset. vcache i this provides power to processor llc and system interface logic. actual value of the voltage is determined by the settings of cvid[7:1]. vcachesense io vr sense lines. (vcache) vcc33 i vcc33 supplies 3.3v to pirom/oem scra tch rom, initrom and level translators. this supply is required both for pirom usage and for correct processor boot operation. vcccore i this provides power to the cores on the processor. actual value of the voltage is determined by the settings of vid[7:0]. vsscoreesense io vr sense lines. (vcore) table 5-1. signal definitions (sheet 5 of 6) name type description
signal definitions 110 datasheet volume 1 of 2 vid[7:0] i/o vid[7:0] is an input only during power on configuration. it is an output signal during normal operation. as an output, vid[7:0] (voltage id) are signals that are used to support automatic selection of power supply voltages (v cc ). refer to the voltage regulator module (vrm) and enterprise voltage regulato r-down (evrd) 11.1 design guidelines for more information. the voltage supply for th ese signals must be valid before the vr can supply v cc to the processor. conversely, the vr output must be disabled until the voltage supply for the vid signals become valid. the vid signals are needed to support the processor voltage specificat ion variations. the vr must supply the voltage that is requested by the signals, or disable itself. as an inputs during power on configuration: vid [7] is an electronic safety key for distinguishing vr11.1 from pmpv6. vid[6] is a spare bit reserved for future use. vid[5:3] - imon bits are output signals for imon gain setting. see voltage regulator module (vrm) and enterprise voltage regulator- down (evrd) 11.1 design guidelines for gain settin g information. vid[2:0] or msid[2:0] - market segment id, or msid are provided to indicate the market segment for the processor and may be used for future processor compatibility or for keying. in addition, msid protects the platform by preventing a higher power processor from booting in a platform designed for lower power processors. this value is latched from the pl atform in to the cpu, on the rising edge of viopwrgood, during the cold boot power up sequence. vio_vid[4:1] o voltage id driven out to the vr 11.1 for dynamic/static adjustment of processor voltage set point. note that these pins are either floated, or tied to ground on the package. vioc i vioc provides power to the input/output interface on the intel xeon processor e7- 8800/4800/2800 product families processor intel? qpi i/o. viof i viof provides power to the input/output interface on the intel xeon processor e7- 8800/4800/2800 product families processor intel? smi i/o. viopowergood i vio power good signal. vreg i ~1.8 v. voltage to plls. vss i vss is the ground plane for the in tel xeon processor e7-8800/4800/2800 product families processor. vsscachesense io vr sense lines. (vcache) table 5-1. signal definitions (sheet 6 of 6) name type description
datasheet volume 1 of 2 111 thermal specifications 6 thermal specifications 6.1 package thermal specifications the intel xeon processor e7-8800/4800/2800 product families processor requires a thermal solution to maintain temperatures within its operating limits. any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. for more information on designing a component level thermal solution, refer to the intel? xeon? processor 7500 series and intel? xeon? processor e7-8800/4800/2800 product families thermal and mechanical design guide . a complete solution includes both compon ent and system level thermal management features. component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader (ihs). typical system level thermal solutions may consist of system fans combined with ducting and venting. 6.1.1 thermal specifications to allow the optimal operation and long-term reliability of intel? processor-based systems, the processor must remain within the minimum and maximum case temperature (t case ) specifications as defined by the applicable thermal profile (see ta b l e 6 - 1 and figure 6-1 for 130w tdp intel xeon processor e7-8800/4800/2800 product families processor, ta b l e 6 - 1 and figure 6-2 for 105w tdp intel xeon processor e7-8800/4800/2800 product families processor, and ta b l e 6 - 1 and figure 6-3 for 95w tdp intel xeon processor e7-8800/4800/2800 product families processor). thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. for more details on thermal solution design, please refer to the intel? xeon? processor 7500 series and intel? xeon? processor e7-8800/4800/2800 product families thermal and mechanical design guide . intel xeon processor e7-8800/4800/2800 product families processor implements a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed co ntrol and to ensure processor reliability. selection of the appropriate fan speed is based on the relative temperature data reported by the processor?s platform environment control interface (peci) bus as described in section 6.3 . the temperature reported over peci is always a negative value and represents a delta below the onset of thermal control circuit (tcc) activation, as indicated by prochot_n (see section 6.2, ?processor thermal features? on page 118 ). systems that implement fan speed control must be designed to use this data. systems that do not alter the fan speed only need to guarantee that the case temperature meets the thermal profile specifications. intel has developed a thermal profile that can be implemented with 130w tdp intel xeon processor e7-8800/4800/2800 product families processor to ensure adherence to intel reliability requirements. the 130w tdp intel xeon processor e7-8800/4800/2800 product families processor thermal profile (see figure 6-1 ; ta b l e 6 - 2 ) is representative of a volumetrically unconstrained thermal solution (that is, industry enabled 4u heatsink). in this scenario, it is expected that the thermal control circuit (tcc) would only be activated for very brief periods of time when running the most power intensive
thermal specifications 112 datasheet volume 1 of 2 applications. intel has developed the therma l profile to allow customers to choose the thermal solution and environmental parameters that best suit their platform implementation. the 105w tdp intel xeon processor e7-8800/4800/2800 product families processor (see figure 6-2 ; ta b l e 6 - 3 ) and 95w tdp intel xeon processor e7-8800/4800/2800 product families processor (see figure 6-3 ; ta b l e 6 - 4 ) support a single thermal profile. the thermal profiles are indicative of a cons trained thermal environment. utilization of a thermal solution that does not meet the thermal profile will violate the thermal specifications and may result in permanent damage to the processor. the upper point of the thermal profile consis ts of the thermal design power (tdp) and the associated t case_max value. it should be noted that the upper point associated with the 130w tdp intel xeon processor e7-8800/4800/2800 product families processor thermal profile (x = tdp and y = t case_max p @ tdp) represents a thermal solution design point. in actuality the processor case temperature may not reach this value due to tcc activation (see figure 6-1 for the performance intel xeon processor e7-8800/ 4800/2800 product families processor). the lowe r point of the thermal profile consists of x = p _profile_min and y = t case_max @ p _profile_min . p _profile_min is defined as the processor power at which t case , calculated from the thermal profile, is equal to 69c. analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. intel recommends that complete thermal solution designs target the thermal design power (tdp) instead of the maximum processor power consumption. the intel? thermal monitor feature is intended to help protect the processor in the event that an application exceeds the tdp recommendation for a sustained time period. fo r more details on this feature, refer to section 6.2 . to ensure maximum flexibility for fu ture requirements, systems should be designed to the flexible motherboard (fmb) guidelines, even if a processor with lower power dissipation is currently planned. th e intel thermal monitor 1 or intel thermal monitor 2 feature must be enabled for the pr ocessor to remain within its specifications . notes: 1. these values are specified at v cc_max for all processor frequencies. syst ems must be designed to ensure the processor is not to be subjected to any static v cc and i cc combination wherein v cc exceeds v cc_max at specified i cc . 2. thermal design power (tdp) should be used for proc essor thermal solution design targets. tdp is not the maximum power that the processor can diss ipate. tdp is measured at maximum t case . 3. these specifications are based on pre-silicon estimates and simulation s. these specifications may be updated with characterized data from silicon measurements in a fu ture release of this document. 4. power specifications are defined at all vids found in ta b l e 2 - 2 . the intel xeon processor e7-8800/4800/ 2800 product families processor may be shippe d under multiple vids for each frequency. 5. fmb, or flexible motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. table 6-1. processor thermal specifications core frequency thermal design power (w) minimum t case (c) maximum t case (c) notes processor launch to fmb 130 5 see figure 6-1 ; ta b l e 6 - 2 ; 1, 2, 3, 4, 5 processor launch to fmb 105 5 see figure 6-2 ; ta b l e 6 - 3 ; 1, 2, 3, 4, 5 processor launch to fmb 95 5 see figure 6-3 ; ta b l e 6 - 4 ; 1, 2, 3, 4, 5
datasheet volume 1 of 2 113 thermal specifications notes: 1. thermal profile is representative of a volu metrically unconstrained platform. refer to ta b l e 6 - 2 for discrete points that constitute the thermal profile. 2. implementation of the thermal profil e should result in virtually no tcc activation. furthermore, utilization of thermal solutions that do not me et processor thermal profile will resu lt in increased probability of tcc activation and may incur measurable performance loss. (see section 6.2 for details on tcc activation.) 3. refer to the intel? xeon? processor 7500 series and intel? xeon? processor e7-8800/4800/2800 product families thermal and mechanical design guide for system and environmental implementation details. figure 6-1. 130w tdp processor thermal profile tbd table 6-2. 130w tdp processor th ermal profile table (sheet 1 of 2) power (w) t case_max ( c) 0 48.0 5 48.8 10 49.6 15 50.4 20 51.2 25 52.0 30 52.8 35 53.6 40 54.4 45 55.2 50 56.0 55 56.8 60 57.6 65 58.4
thermal specifications 114 datasheet volume 1 of 2 notes: 1. thermal profile is representative of a vo lumetrically constrained platform. refer to ta b l e 6 - 3 for discrete points that constitute the thermal profile. 2. implementation of the thermal profile should result in virtually no tcc activation. furthermore, utilization of thermal solutions that do not me et processor thermal profile will resu lt in increased probability of tcc activation and may incur measurable performance loss. (see section 6.2 for details on tcc activation.) 3. refer to the intel? xeon? processor 7500 series and intel? xeon? processor e7-8800/4800/2800 product families thermal and mechanical design guide for system and environmental implementation details. 70 59.1 75 59.9 80 60.7 85 61.5 90 62.3 95 63.1 100 63.9 105 64.7 110 65.5 115 66.3 120 67.1 125 67.9 130 69.0 figure 6-2. 105w tdp pr ocessor thermal profile table 6-2. 130w tdp processor th ermal profile table (sheet 2 of 2) power (w) t case_max ( c) tbd y = .179x + 45.2 40.0 45.0 50.0 55.0 60.0 65.0 70.0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 power [w] temperature [c] tcase_max is a thermal solution design point
datasheet volume 1 of 2 115 thermal specifications table 6-3. 105w tdp proce ssor thermal profile table power (w) t case_max ( c) 0 45.2 5 46.1 10 47.0 15 47.9 20 48.8 25 49.7 30 50.6 35 51.5 40 52.4 45 53.3 50 54.1 55 55.0 60 55.9 65 56.8 70 57.7 75 58.6 80 59.5 85 60.4 90 61.3 95 62.2 100 63.1 105 64.0
thermal specifications 116 datasheet volume 1 of 2 notes: 1. thermal profile is representative of a vo lumetrically constrained platform. refer to ta b l e 6 - 4 for discrete points that constitute the thermal profile. 2. implementation of the thermal profile should result in virtually no tcc activation. furthermore, utilization of thermal solutions that do not me et processor thermal profile will resu lt in increased probability of tcc activation and may incur measurable performance loss. (see section 6.2 for details on tcc activation.) 3. refer to the intel? xeon? processor 7500 series and intel? xeon? processor e7-8800/4800/2800 product families thermal and mechanical design guide for system and environmental implementation details. figure 6-3. 95w tdp pr ocessor thermal profile tbd table 6-4. 95w tdp processor ther mal profile table (sheet 1 of 2) power (w) t case_max ( c) 0 48.2 5 49.3 10 50.5 15 51.6 20 52.8 25 53.9 30 55.1 35 56.2 40 57.4 45 58.5 50 59.7 55 60.8 60 62.0 65 63.1 70 64.3
datasheet volume 1 of 2 117 thermal specifications 6.1.2 thermal metrology the minimum and maximum case temperatures (t case ) are specified in ta b l e 6 - 2 through ta b l e 6 - 4 , and are measured at the geometric top center of the processor substrate, not ihs, as in previous products. figure 6-4 illustrates the location where t case temperature measurements should be made. for detailed guidelines on temperature measurement methodology, refer to the intel? xeon? processor 7500 series and intel? xeon? processor e7-8800/4800/2800 product families thermal and mechanical design guide . note: figure is not to scale and is for reference only. 75 65.4 80 66.6 85 67.7 90 68.9 95 70.0 table 6-4. 95w tdp processor ther mal profile table (sheet 2 of 2) power (w) t case_max ( c) figure 6-4. case temperature (t case ) measurement location tbd
thermal specifications 118 datasheet volume 1 of 2 6.2 processor thermal features 6.2.1 thermal monitor features the intel xeon processor e7-8800/4800/2800 product families processor provides two thermal monitor features, intel thermal moni tor 1 (?tm1?) and intel thermal monitor 2 (?tm2?). both intel thermal monitor 1 and 2 must be enabled in bios for the processor to be operating within specifications. when both are enabled, intel thermal monitor 2 will be activated first and intel thermal monitor 1 will be added if intel thermal monitor 2 is not effective. 6.2.2 intel ? thermal monitor 1 the intel thermal monitor 1 feature helps control the processor temperature by activating the thermal control circuit (tcc) when the processor silicon reaches its maximum operating temperature. the tcc reduces processor power consumption as needed by modulating (starting and stopping ) the internal processor core clocks. intel thermal monitor 1 or intel thermal monitor 2 must be enabled for the processor to be operating within specifications. the temp erature at which intel thermal monitor 1 activates the thermal control circuit is not user-configurable and is not software-visible. bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the tcc is active. when intel thermal monitor 1 is enabled, and a high temperature situation exists (that is, tcc is active), the clocks will be modula ted by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30 - 50%). cycle times are processor speed dependent and will decrease as processor core frequencies increase. a small amount of hysteresis has been included to prevent rapid active/inactive transitions of the tcc when the processor temperature is near its maximum operating temperature. once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the tcc goes inactive and clock modulation ceases. with a thermal solution designed to meet the intel xeon processor e7-8800/4800/2800 product families processor thermal profiles, it is anticipated that the tcc would only be activated for very short periods of time when running the most power-intensive applications. the processor performance impact due to these brief periods of tcc activation is expected to be so minor that it would be immeasurable. in addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the tcc is active continuously. the duty cycle for the tcc, when activated by the intel thermal monitor 1, is factory- configured and cannot be modified. intel thermal monitor 1 does not require any additional hardware, software drivers, or interrupt handling routines. 6.2.3 intel thermal monitor 2 the intel xeon processor e7-8800/4800/2800 product families processor adds supports for an enhanced thermal monitor capability known as intel thermal monitor 2. this mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor. intel thermal monitor 1 or intel thermal monitor 2 must be enabled for the processor to be operating within specifications. intel thermal monitor 2 requires support for dynamic vid transitions in the platform.
datasheet volume 1 of 2 119 thermal specifications when intel thermal monitor 2 is enabled, an d a high temperature situation is detected, the thermal control circuit (tcc) will be activated for all processor cores. the tcc causes the processor to adjust its operat ing frequency (via the bus multiplier) and input voltage (via the vid signals). this combination of reduced frequency and vid results in a reduction to the processor power consumption. the lowest bus multiplier for the intel thermal monitor 2 is 8:1. this results in an operating frequency of 1066 mhz. once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new vid code to the voltage regulator. the voltage regulator must support dynamic vid steps in order to support the intel thermal monitor 2. during the voltage change, it will be necessary to transition through multiple vid codes to reach the target operating voltag e. each step will be one or two vid table entries (see ta b l e 2 - 2 ). the processor continues to execute instructions during the voltage transition. operation at the lower voltage reduces the power consumption of the processor. a small amount of hysteresis has been included to prevent rapid active/inactive transitions of the tcc when the processor temperature is near its maximum operating temperature. once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. transition of the vid code will occur first, in order to ensure proper operation once the processor reaches its normal operating frequency. refer to figure 6-5 for an illustration of this ordering. the prochot_n signal is asserted when a high-temperature situation is detected, regardless of whether intel thermal monitor 1 or intel thermal monitor 2 is enabled. 6.2.4 on-demand mode the processor provides an auxiliary mechanis m that allows system software to force the processor to reduce its power consumption. this mechanism is referred to as ?on-demand? mode and is distinct from th e intel thermal monitor 1 and intel thermal monitor 2 features. on-demand mode is inte nded as a means to reduce system level power consumption. systems utilizing intel xeon processor e7-8800/4800/2800 product families processor must not rely on software usage of this mechanism to limit the processor temperature. there are two wa ys to implement on-demand mode. if bit figure 6-5. intel? thermal monitor 2 frequency and voltage ordering vcc temperature v nom frequency time f tm2 f max t tm2 v tm2 t(hysterisis) vcc temperature v nom frequency time f tm2 f max t tm2 v tm2 t(hysterisis)
thermal specifications 120 datasheet volume 1 of 2 4 of the ia32_clock_modulation msr is set to a ?1?, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. also, a write the p_cnt i/o address, the processor will immediately reduce power consumptions as well. the p_cnt i/o address write controls all acti ve cores. the msr write only impacts the core that performed the msr write. the p_cn t i/o address write takes priority over the msr write. when using on-demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ia32_clock_modulation msr. in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments. on-demand mode may be used in conjunction with the thermal monitor; however, if the system tries to en able on-demand mode at the same time the tcc is engaged, the factory configured duty cycle of the tcc will override the duty cycle selected by the on-demand mode. 6.2.5 prochot_n signal an external signal, prochot_n (processor ho t) is asserted when the temperature of any processor core has reached its factory configured trip point. if intel thermal monitor 1 and intel thermal monitor 2 are enabled (note that intel thermal monitor 1 and intel thermal monitor 2 must be enabled for the processor to be operating within specification), the tcc will be active wh en prochot_n is asserted. intel thermal monitor 2 activates first, and intel thermal mo nitor 1 activates only if needed to further reduce temperature. the processor can be co nfigured to generate an interrupt upon the assertion or de-assertion of prochot_n. refer to the intel ? 64 and ia-32 architectures software developer?s manual and the intel? xeon? processor 7500 series datasheet volume 2 for specific register and programming details. prochot_n is designed to assert at or a few degrees higher than maximum t case (as specified by thermal profile) when dissipating tdp power, and cannot be interpreted as an indication of processor case temperature. this temperature delta accounts for processor package, lifetime and manufacturing variations and attempts to ensure the thermal control circuit is not activated below maximum t case when dissipating tdp power. there is no defined or fixed correlation between the prochot_n trip temperature, or the case temperature. th ermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of t case , or prochot_n. this signal is only valid wh en power good is asserted, and cpu reset is not asserted. 6.2.6 force_pr_n signal the force_pr_n (force power reduction) input can be used by the platform to cause intel xeon processor e7-8800/4800/2800 product families processor to activate the tcc. if the thermal monitor is enabled, the tcc will be activated upon the assertion of the force_pr_n signal. force_pr_n is an asynchronous input. assertion of the force_pr_n signal will activate tcc for all operating processor cores. the tcc will remain active until the system deasserts force_pr_n. force_pr_n can be used to thermally protect other system components. to use the vr as an example, when force_pr_n is asserted, the tcc circuit in the processor will activate, reducing the current consumption of the processor and the corresponding temperature of the vr.
datasheet volume 1 of 2 121 thermal specifications it should be noted that assertion of force_pr_n does not automatically assert prochot_n. as mentioned previously, the prochot_n signal is asserted when a high temperature situation is detected. a minimum pulse width of 500 s is recommended when force_pr_n is asserted by the system . sustained activation of the force_pr_n signal may cause noticeable platform performance degradation. 6.2.7 thermtrip_n signal regardless of whether or not the intel thermal monitor 1 or 2 is enabled, in the event of a catastrophic cooling failure, the proce ssor will automatically shut down when any core has reached an elevated temperature (refer to the thermtrip_n definition in ta b l e 5 - 1 ). at this point, the sideband signal thermtrip_n will go active and stay active as described in ta b l e 5 - 1 . thermtrip_n activation is independent of processor activity. if thermtrip_n is asserted, processor core voltage (v cc ) and processor cache voltage (vcache) must be removed within the time frame defined. this signal is only valid when power good is asserted, and cpu reset is not asserted. 6.2.8 thermalert_n signal the thermalert_n pin activates when a pre-programmed temperature is reached on any of the device cores. this pre-programmed temperature is an offset from prochot, an programmed via bios. there is no sign for the value, as it is always assumed that the values is less than or equal to prochot. when not programmed, the value is zero. the expected usage for this signal is in fan speed control when direct peci readings are not used. note that all thermal specifications must be met when using this signal as part of an over all thermal solution. this signal is only valid when power good is asserted, cpu reset is not asserted, and bios has configured the thermalert thresh old temperature. note that bios can not configure the thermalert threshold until the processor is out of reset. 6.3 platform environment control interface (peci) the platform environment control interface (peci) uses a single wire for self-clocking and data transfer. the bus requires no additi onal control lines. the physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. the duration of the signal driven high depends on whether the bit value is a logic ?0? or logic ?1?. peci also includes variable data transfer rate established with every message. in this way, it is highly flexible even though underlying logic is simple. the interface design was optimized for inte rfacing to intel? processor and chipset components in both single processor and multiple processor environments. the single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operat ing conditions and configuration information. the peci bus offers: ? a wide speed range from 2 kbps to 2 mbps ? crc check byte used to efficiently and atomically confirm accurate data delivery ? synchronization at the beginning of every message minimizes device timing accuracy requirements
thermal specifications 122 datasheet volume 1 of 2 what follows is a processor-specific peci client definition, and is largely an addendum to the peci network layer and design recommendations sections for the peci 2.0 specification document. note: note that the peci commands described in this document apply to the intel xeon processor e7-8800/4800/2800 product families processor only. refer to ta b l e 6 - 5 for a list of peci commands supported by the intel xeon processor e7-8800/4800/2800 product families processor peci client. note: 1. refer to ta b l e 6 - 9 for a summary of mailbox commands supported by the intel xeon processor e7-8800/ 4800/2800 product families processor cpu. 6.3.1 peci client capabilities the intel xeon processor e7-8800/4800/2800 product families processor peci client is designed to support the following sideband functions: ? processor and dram thermal management ? platform manageability functions, includin g thermal, power and electrical error monitoring ? processor interface tuning and diagnostics capabilities (intel ? interconnect bist [intel ? ibist]). 6.3.1.1 thermal management processor fan speed control is managed by comparing peci thermal readings against the processor-specific fan speed control reference point, or t control . both t control and peci thermal readings are accessible via the processor peci client. these variables are referenced to a common temperature, the tcc activation point, and are both defined as negative offsets from that refe rence. algorithms for fan speed management using peci thermal readings and the t control reference are documented in section 6.3.2.6 . peci-based access to dram thermal readings and throttling control coefficients provide a means for board management controllers (bmcs) or other platform management devices to feed hints into on-die memory controller throttling algorithms. these control coefficients are accessible using pci config uration space writes via peci. the peci- based configuration write functionality is defined in section 6.3.2.5 . table 6-5. summary of proce ssor-specific peci commands command supported on intel xeon processor e7-8800 /4800/2800 product families processor cpu ping() yes getdib() yes gettemp() yes pciconfigrd() yes pciconfigwr() yes mbxsend() 1 yes mbxget() 1 yes
datasheet volume 1 of 2 123 thermal specifications 6.3.1.2 platform manageability peci allows full read access to error and status monitoring registers within the processor?s pci configuration space. it also provides insight into thermal monitoring functions such as tcc activation timers and thermal error logs. 6.3.1.3 processor interface tuning and diagnostics the intel xeon processor e7-8800/4800/2800 product families processor intel ibist allows for in-field diagnostic capabilities in intel qpi and memory controller interfaces. peci provides a port to execute these diagnostics via its pci configuration read and write capabilities. 6.3.2 client command suite 6.3.2.1 ping() ping() is a required message for all peci devices. this message is used to enumerate devices or determine if a device has been removed, been powered-off, etc. a ping() sent to a device address always returns a non-zero write fcs if the device at the targeted address is able to respond. 6.3.2.1.1 command format the ping() format is as follows: write length: 0 read length: 0 an example ping() command to peci device address 0x30 is shown below. 6.3.2.2 getdib() the processor peci client implementation of getdib() includes an 8-byte response and provides information regarding client revision number and the number of supported domains. all processor peci clients support the getdib() command. figure 6-6. ping() byte # byte definition 0 client address 1 write length 0x00 2 read length 0x00 3 fcs figure 6-7. ping() example byte # byte definition 0 0x30 1 0x00 2 0x00 3 0xe1
thermal specifications 124 datasheet volume 1 of 2 6.3.2.2.1 command format the getdib() format is as follows: write length: 1 read length: 8 command: 0xf7 6.3.2.2.2 device info the device info byte gives details regarding the peci client configuration. at a minimum, all clients supporting getdib w ill return the number of domains inside the package via this field. with any client, at least one domain (domain 0) must exist. therefore, the number of domains reported is defined as the number of domains in addition to domain 0. for example, if the number 0b1 is returned, that would indicate that the peci client supports two domains. 6.3.2.2.3 revision number all clients that support the getdib command also support revision number reporting. the revision number may be used by a host or originator to manage different command suites or response codes from the client. revision number is always reported in the second byte of the getdib() response. th e revision number always maps to the revision number of this document. figure 6-8. getdib() byte # byte definition 0 client address 1 write length 0x01 2 read length 0x08 4 fcs 3 cmd code 0xf7 5 device info 6 revision number 7 reserved 8 reserved 9 reserved 10 reserved 11 reserved 12 reserved 13 fcs figure 6-9. device info field definition reserved # of domains reserved 76543210
datasheet volume 1 of 2 125 thermal specifications 6.3.2.3 gettemp() the gettemp() command is used to retrieve the temperature from a target peci address. the temperature is used by the external thermal management system to regulate the temperature on the die. the data is returned as a negative value representing the number of degrees centig rade below the thermal control circuit activation temperature of the peci device. note that a value of zero represents the temperature at which the thermal control circuit activates. the actual value that the thermal management system uses as a control set point (tcontrol) is also defined as a negative number below the thermal control circuit activation temperature. tcontrol may be extracted from the processor by issuing a peci mailbox mbxget() (see section 6.3.2.8 ), or using a rdmsr instruction. refer to section 6.3.6 for details regarding temperature data formatting. 6.3.2.3.1 command format the gettemp() format is as follows: write length: 1 read length: 2 command: 0x01 multi-domain support: yes (see ta b l e 6 - 1 5 ) description : returns the current temperature fo r addressed processor peci client. figure 6-10. revision number definition 0 3 4 7 major revision# minor revision# figure 6-11. gettemp() byte # byte definition 0 client address 1 write length 0x01 2 read length 0x02 4 fcs 5 temp[7:0] 6 temp[15:8] 7 fcs 3 cmd code 0x01
thermal specifications 126 datasheet volume 1 of 2 example bus transaction for a thermal sensor device located at address 0x30 returning a value of negative 10c: 6.3.2.3.2 supported responses the typical client response is a passing fcs and good thermal data. under some conditions, the client?s response will indicate a failure. 6.3.2.4 pciconfigrd() the pciconfigrd() command gives sideband re ad access to the entire pci configuration space maintained in the processor. this ca pability does not include support for route- through to downstream devices or sibling processors. the exact listing of supported devices, functions, and registers can be found in the intel? xeon? processor 7500 series datasheet volume 2 . peci originators may conduct a device/function/register enumeration sweep of this space by issu ing reads in the same manner that bios would. a response of all 1?s indicates that the device/function/register is unimplemented. pci configuration addresses are constructed as shown in the following diagram. under normal in-band procedures, the bus number (including any reserved bits) would be used to direct a read or write to the proper device. since there is a one-to-one mapping between any given client address and the bus number, any request made with a bad bus number is ignored and the client will resp ond with a ?pass? completion code but all 0?s in the data. the only legal bus number is 0x00. the client will return all 1?s in the data response and ?pass? for the completion code for all of the following conditions: ? unimplemented device ? unimplemented function ? unimplemented register figure 6-12. gettemp() example byte # byte definition 0 0x30 1 0x01 2 0x02 4 0xef 5 0x80 6 0xfd 7 0x4b 3 0x01 table 6-6. gettemp() response definition response meaning general sensor error (gse) thermal scan did not complete in time. retry is appropriate. 0x0000 processor is running at its maximu m temperature or is currently being reset. all other data valid temperature reading, repo rted as a negative offset from the tcc activation temperature. figure 6-13. pci configuration address 31 reserved 27 28 20 19 15 11 14 12 0 bus device function register
datasheet volume 1 of 2 127 thermal specifications pci configuration reads may be issued in byte, word, or dword granularities. 6.3.2.4.1 command format the pciconfigrd() format is as follows: write length: 5 read length: 2 (byte data), 3 (word data), 5 (dword data) command: 0xc1 multi-domain support: yes (see ta b l e 6 - 1 5 ) description : returns the data maintained in the pci configuration space at the pci configuration address sent. the read length dictates the desired data return size. this command supports byte, word, and dword resp onses as well as a completion code. all command responses are prepended with a comp letion code that includes additional pass/fail status information. refer to section 6.3.4.2 for details regarding completion codes. note that the 4-byte pci configuration addre ss defined above is sent in standard peci ordering with lsb first and msb last. 6.3.2.4.2 supported responses the typical client response is a passing fcs, a passing completion code (cc) and valid data. under some conditions, the client?s response will indicate a failure. figure 6-14. pciconfigrd() byte # byte definition 0 client address 1 write length 0x05 2 read length {0x02,0x03,0x05} 8 fcs 3 cmd code 0xc1 9 completion code 10 data 0 ... 8+rl data n 9+rl fcs 4 5 6 7 lsb msb pci configuration address table 6-7. pciconfigrd () response definition response meaning abort fcs illegal command formatting (mismatched rl/wl/command code) cc: 0x40 command passed, data is valid cc: 0x80 error causing a response timeout. either due to a rare, internal timing condition or a processor reset or processor s1 state. retry is appropriate outside of the reset or s1 states.
thermal specifications 128 datasheet volume 1 of 2 6.3.2.5 pciconfigwr() the pciconfigwr() command gives sideband write access to the pci configuration space maintained in the processor. the exact listing of supported devices, functions is defined in the intel? xeon? processor 7500 series datasheet volume 2 . peci originators may conduct a device/function/register enumeration sweep of this space by issuing reads in the same manner that bios would. pci configuration addresses are constructed as shown in figure 6-13 , and this command is subject to the same address configuration rules as defined in section 6.3.2.4 . pci configuration reads may be issued in byte, word, or dword granularities. because a pciconfigwr() results in an update to potentially critical registers inside the processor, it includes an assured write fcs (aw fcs) byte as part of the write data payload. in the event that the aw fcs mism atches with the client-calculated fcs, the client will abort the write and will always respond with a bad write fcs. 6.3.2.5.1 command format the pciconfigwr() format is as follows: write length: 7 (byte), 8 (word), 10 (dword) read length: 1 command: 0xc5 multi-domain support: yes (see ta b l e 6 - 1 5 ) description : writes the data sent to the requested register address. write length dictates the desired write granularity. the command always returns a completion code indicating the pass/fail status informat ion. write commands issued to illegal bus numbers, or unimplemented device / function / register addresses are ignored but return a passing completion code. refer to section 6.3.4.2 for details regarding completion codes. figure 6-15. pciconfigwr() byte # byte definition 0 client address 1 write length {0x07,0x08,0x10} 2 read length 0x01 wl+1 fcs 3 cmd code 0xc5 wl+2 completion code wl+3 fcs 4 5 6 7 lsb msb pci configuration address 8 wl-1 lsb msb data (1, 2 or 4 bytes) wl aw fcs
datasheet volume 1 of 2 129 thermal specifications note that the 4-byte pci configuration ad dress and data defined above are sent in standard peci ordering with lsb first and msb last. 6.3.2.5.2 supported responses the typical client response is a passing fcs, a passing completion code and valid data. under some conditions, the client?s response will indicate a failure. 6.3.2.6 mailbox the peci mailbox (?mbx?) is a generic interf ace to access a wide variety of internal processor states. a mailbox request consists of sending a 1-byte request type and 4-byte data to the processor, followed by a 4-byte read of the response data. the following sections describe the mailbox capabilities as well as the usage semantics for the mbxsend and mbxget commands which are used to send and receive data. 6.3.2.6.1 capabilities table 6-8. pciconfigwr( ) response definition response meaning bad fcs electrical error or aw fcs failure abort fcs illegal command formatting (mismatched rl/wl/command code) cc: 0x40 command passed, data is valid cc: 0x80 error causing a response timeout. either due to a rare, internal timing condition or a processor reset condition or processor s1 state. retry is appropriate outside of the reset or s1 states. table 6-9. mailbox command summary (sheet 1 of 2) command name request type code (byte) mbxsend data (dword) mbxget data (dword) description ping 0x00 0x00 0x00 verify the operability / existence of the mailbox. thermal status read/clear 0x01 log bit clear mask thermal status register read the thermal status register and optionally clear any log bits. the thermal status has status and log bits indicating the state of processor tcc activation, extern al forcepr_n assertion, and critical temperature threshold crossings. counter snapshot 0x03 0x00 0x00 snapshots all peci-based counters counter clear 0x04 0x00 0x00 concurrently clear and restart all counters. counter read 0x05 counter number counter data returns the counter number requested. 0: total reference time 1: total tcc activation time counter icc-tdc read 0x06 0x00 icc-tdc returns the specified icc-tdc of this part, in amps. thermal config data read 0x07 0x00 thermal config data reads the thermal averaging constant. thermal config data write 0x08 thermal config data 0x00 writes the thermal averaging constant. tcontrol read 0x09 0x00 tcontrol reads the fan speed control reference temperature, tcontrol, in peci temperature format. t-state throttling control read 0xb 0x00 acpi t-state control word reads the peci acpi t-state throttling control word.
thermal specifications 130 datasheet volume 1 of 2 any mbxsend request with a request type not defined in ta b l e 6 - 9 will result in a failing completion code. more detailed command definitions follow. 6.3.2.6.2 ping the mailbox interface may be checked by issuing a mailbox ?ping? command. if the command returns a passing completion code, it is functional. under normal operating conditions, the mailbox ping command should always pass. 6.3.2.6.3 thermal status read / clear the thermal status read provides information on package level thermal status. data includes: ? the status of tcc activation / prochot_n output ? forcepr_n input ?critical temperature these status bits are a subset of the bits defined in the ia32_therm_status msr on the processor, and more details on the meaning of these bits may be found in the intel ? 64 and ia-32 architectures software developer?s manual , vol. 3b. both status and sticky log bits are managed in this status word. all sticky log bits are set upon a rising edge of the associated stat us bit, and the log bits are cleared only by thermal status reads or a processor reset. a read of the thermal status word always includes a log bit clear mask that allows the host to clear any or all log bits that it is interested in tracking. a bit set to 0b0 in the log bit clear mask will re sult in clearing the associated log bit. if a mask bit is set to 0b0 and that bit is not a legal mask, a failing completion code will be returned. a bit set to 0b1 is ignored and results in no change to any sticky log bits. for example, to clear the tcc activation log bit and retain all other log bits, the thermal status read should send a mask of 0xfffffffd. t-state throttling control write 0xc acpi t- state control word 0x00 writes the peci acpi t- state throttling control word. average tem pe ra t ur e read 0x21 0x00 average te m p e ra t u r e value intel xeon processor e7-8800/4800/2800 product families processor only: reads the average temperature of all cores in peci temperature format. get uncore tem pe ra t u r e 0x22 0x00 get _uncore_ te m p reads the uncore temperature in peci format. write p-state limit 0x23 0x00 write_p_sta te_limit sets an upper limit for p-state frequency ratio. read p-state limit 0x24 0x00 read_p_stat e_limit reads the programmed p-state limit if set. table 6-9. mailbox command summary (sheet 2 of 2) command name request type code (byte) mbxsend data (dword) mbxget data (dword) description
datasheet volume 1 of 2 131 thermal specifications 6.3.2.6.4 counter snapshot / read / clear a reference time and ?thermally constrained? time are managed in the processor. these two counters are managed via the mailbox. these counters are valuable for detecting thermal runaway conditions where the tcc activation duty cycle reaches excessive levels. the counters may be simultaneously snapshot, simultaneously cleared, or independently read. the simultaneous snapsh ot capability is provided in order to guarantee concurrent reads even with signific ant read latency over the peci bus. each counter is 32-bits wide. 6.3.2.6.5 icc-tdc read icc-tdc is the intel xeon processor e7-8800/4800/2800 product families processor tdc current draw specification. this data ma y be used to confirm matching icc profiles of processors in mp configurations. it may also be used during the processor boot sequence to verify processor compatibility with motherboard icc delivery capabilities. this command returns icc-tdc in units of 1 amp. 6.3.2.6.6 thermal data config read / write the thermal data configuration register allows the peci host to control the window over which thermal data is filtered. the default window is 256 ms. the host may configure this window by writing a thermal filtering constant as a power of two. e.g., sending a value of 9 results in a filtering window of 2 9 or 512 ms. figure 6-16. thermal status word table 6-10. counter definition counter name counter number definition total time 0x00 counts the total time the processor has been executing with a resolution of approximately 1ms. this counter wraps at 32 bits. thermally constrained time 0x01 counts the total time the processor has been operating at a lowered performance due to tcc ac tivation. this timer includes the time required to ramp back up to the original p-state target after tcc activation expires. this timer does not include tcc activation time as a result of an external assertion of forcepr_n.
thermal specifications 132 datasheet volume 1 of 2 6.3.2.6.7 tcontrol read tcontrol is used for fan speed control management. the tcontrol limit may be read over peci using this mailbox functi on. unlike the in-band msr interface, this tcontrol value is already adjusted to be in the native peci temperature format of a 2-byte, 2?s complement number. 6.3.2.6.8 t-state throttling control read / write peci offers the ability to enable and conf igure acpi t-state (core clock modulation) throttling. acpi t-state throttling forces all cpu cores into duty cycle clock modulation where the core toggles between c0 (clocks on) and c1 (clocks off) states at the specified duty cycle. this throttling reduces cpu performance to the duty cycle specified and, more importantly, re sults in processor power reduction. the intel xeon processor e7-8800/4800/2800 product families processor supports software initiated t-state throttling and automatic t-state throttling as part of the internal thermal monitor response mechanism (upon tcc activation). the peci t-state throttling control register read/write capabilit y is managed only in the peci domain. in- band software may not manipulate or read the peci t-state control setting. in the event that multiple agents are requesting t-state throttling simultaneously, the cpu always gives priority to the lowest power setting, or the numerically lowest duty cycle. on intel xeon processor e7-8800/4800/2800 product families processors, the only supported duty cycle is 12.5% (12.5% clocks on, 87.5% clocks off). it is expected that t-state throttling will be engaged only under emergency thermal or power conditions. future products may support more duty cycles, as defined in the following table: figure 6-17. thermal data configuration register 43 0 thermal filter const reserved 3 1 table 6-11. acpi t-state duty cycle definition duty cycle code definition 0x0 undefined 0x1 12.5% clocks on / 87.5% clocks off 0x2 25% clocks on / 75% clocks off 0x3 37.5% clocks on / 62.5% clocks off 0x4 50% clocks on / 50% clocks off 0x5 62.5% clocks on / 37.5% clocks off 0x6 75% clocks on / 25% clocks off 0x7 87.5% clocks on / 12.5% clocks off
datasheet volume 1 of 2 133 thermal specifications the t-state control word is defined as follows: 6.3.2.6.9 average temperature read the average temperature read mailbox command implemented by intel? xeon? processor 7500 series provides an alternativ e temperature assessment to that provided by the gettemp() peci command. where gettemp() returns the average of the hottest sense points on the processor, the average temp read returns the average of all core temperature sense points. the values from ea ch sensor are averaged and filtered. the data is returned as a negative value representing the number of degrees centigrade below the thermal control circuit activation temperature of the peci device 6.3.2.6.10 get uncore temperature the get uncore temperature command implemented by the processor is used to retrieve the uncore temperature from a target peci address. the temperature can be used as an added input to the external th ermal management system to regulate the temperature on the die. the data is return ed as a negative value representing the number of degrees centigrade below the thermal control circuit activation temperature of the peci device. note that a value of zero represents the temperature at which the thermal control circuit activates. the actual value that the thermal management system uses as a control set point (tcontrol) is also defined as a negative number below the thermal control circuit activation temperature. 6.3.2.6.11 write p-state limit this command creates a p-state frequency upper limit for os requested p-states per socket. the default value for this variable will correspond to p0 for intel xeon processor e7-8800/4800/2800 product families processors which support intel turbo boost technology, and p1 for the remaining intel xeon processor e7-8800/4800/2800 product families processors. any request for a frequency greater than p1 will be taken as a request to have all available p-states enabled. depending on the current package operating st ate, using this function may lead to a p- state transition. the intel xeon processor e7-8800/4800/2800 product families processor expects a mailbox sideband limit request as a core cl ock multiplier ratio corresponding to a valid p-state defined in the acpi table (acpi table is visible to peci host controller). the intel xeon processor e7-8800/4800/2800 product families processor supports clock ratios between maxnonturboratio (p1)+1 and maxefficiencyratio (pn) as allowable p-state requests, but it may expose only selective clock ratios as valid p- states in the acpi table. figure 6-18. acpi t-state throttling control read / write definition enable duty cycle reserved 70 0xb / 0xc request type request data 543 10 7 1 2 3 4 byte # 0 data
thermal specifications 134 datasheet volume 1 of 2 should a requested value be below pn, it will be clamped at pn. should a requested value be greater than p1, the value will be clipped to p1+1 for those intel xeon processor e7-8800/4800/2800 product families processors which support intel turbo boost technology, and p1 for those which do not. this setting is persistent across warm resets. 6.3.2.6.12 read p-state limit this mailbox command is used by the peci host to read out a socket's current sideband p-state frequency ratio upper limit. if the value written is greater than allowed by the acpi table, the largest legal value will be re turned. if the value written is lower than allowed by the acpi table, the lowest lega l value will be returned. a value of p1+1 indicates enabling of all available p-states. 6.3.2.7 mbxsend() the mbxsend() command is utilized for se nding requests to the generic mailbox interface. those requests are in turn serv iced by the processor with some nominal latency and the result is deposited in the mailbox for reading. mbxget() is used to retrieve the response and details are documented in section 6.3.2.8 . the details of processor mailbox capabilities are described in section 6.3.2.6.1 , and many of the fundamental concepts of mailbox ownership, release, and management are discussed in section 6.3.2.9 . 6.3.2.7.1 write data regardless of the function of the mailbox co mmand, a request type modifier and 4-byte data payload must be sent. for mailbox commands where the 4-byte data field is not applicable (for example, the command is a read), the data written should be all zeroes. because a particular mbxsend() command may sp ecify an update to potentially critical registers inside the processor, it includes an assured write fcs (aw fcs) byte as part of the write data payload. in the event that the aw fcs mismatches with the client- calculated fcs, the client will abort the write and will always respond with a bad write fcs. 6.3.2.7.2 command format the mbxsend() format is as follows: write length: 7 read length: 1 command: 0xd1 multi-domain support: yes (see ta b l e 6 - 1 5 ) figure 6-19. mbxsend() command data format byte # byte definition 0 request type 1 data[31:0] 234
datasheet volume 1 of 2 135 thermal specifications description : deposits the request type and associated 4-byte data in the mailbox interface and returns a completion code byte with the details of the execution results. refer to section 6.3.4.2 for completion code definitions. note that the 4-byte data defined above is se nt in standard peci ordering with lsb first and msb last. if the mbxsend() response returns a bad re ad fcs, the completion code can't be trusted and the semaphore may or may not be taken. in order to clean out the interface, an mbxget() must be issued an d the response data should be discarded. 6.3.2.8 mbxget() the mbxget() command is utilized for retrie ving response data from the generic mailbox interface as well as for unlockin g the acquired mailbox. please refer to section 6.3.2.7 for details regarding the mbxsend() command. many of the fundamental concepts of mailbox ownershi p, release, and management are discussed in section 6.3.2.9 . 6.3.2.8.1 write data the mbxget() command is designed to retrieve response data from a previously deposited request. in order to guarantee alignment between the temporally separated request (mbxsend) and response (mbxget) commands, the originally granted transaction id (sent as part of the passing mbxsend() completion code) must be issued as part of the mbxget() request. figure 6-20. mbxsend() byte # byte definition 0 client address 1 write length 0x07 2 read length 0x01 10 fcs 3 cmd code 0xd1 11 completion code 12 fcs 5 6 7 8 lsb msb data[31:0] 10 11 9 aw fcs 4 request type table 6-12. mbxsend() response definition response meaning bad fcs electrical error cc: 0x4x semaphore is granted with a transaction id of ?x? cc: 0x80 error causing a response timeout. either due to a rare, internal timing condition or a processor reset condition or processor s1 state. retry is appropriate outside of the reset or s1 states. cc: 0x86 mailbox interface is unavailable or busy
thermal specifications 136 datasheet volume 1 of 2 any mailbox request made with an illegal or unlocked transaction id will get a failed completion code response. if the transaction id matches an outstanding transaction id associated with a locked mailbox, the command will complete successfully and the response data will be returned to the originator. unlike mbxsend(), no assured write protocol is necessary for this command because this is a read-only function. 6.3.2.8.2 command format the mbxget() format is as follows: write length: 2 read length: 5 command: 0xd5 multi-domain support: yes (see ta b l e 6 - 1 5 ) description : retrieves response data from mailbox and unlocks / releases that mailbox resource. note that the 4-byte data response defined above is sent in standard peci ordering with lsb first and msb last. figure 6-21. mbxget() response data[31:0] byte # byte definition 0 client address 1 write length 0x02 2 read length 0x05 10 fcs 3 cmd code 0xd5 11 completion code 5 6 lsb msb 5 6 4 transaction id 10 11 5 6 8 9 7 10 fcs 11 table 6-13. mbxget() response definition response meaning aborted write fcs response data is not ready. command retry is appropriate. cc: 0x40 command passed, data is valid cc: 0x80 error causing a response timeout. either due to a rare, internal timing condition or a processor reset condition or processor s1 state. retry is appropriate outside of the reset or s1 states. cc: 0x81 thermal configuration data was malformed or exceeded limits. cc: 0x82 thermal status mask is illegal cc: 0x83 invalid counter select cc: 0x84 invalid machine check bank or index
datasheet volume 1 of 2 137 thermal specifications 6.3.2.9 mailbox usage definition 6.3.2.9.1 acquiring the mailbox the mbxsend() command is used to acquire control of the peci mailbox and issue information regarding the specific request. the completion code response indicates whether or not the originator has acquired a lock on the mailbox, and that completion code always specifies the transaction id associated with that lock (see section 6.3.2.9.2 ). once a mailbox has been acquired by an orig inating agent, future requests to acquire that mailbox will be denied with an ?int erface busy? completion code response. the lock on a mailbox is not achieved until the last bit of the mbxsend() read fcs is transferred (in other words, it is not committed until the command completes). if the host aborts the command at any time prior to that bit transmission, the mailbox lock will be lost and it will remain available for any other agent to take control. 6.3.2.9.2 transaction id for all mbxsend() commands that complete successfully, the passing completion code (0x4x) includes a 4-bit transaction id (?x?). that id is the key to the mailbox and must be sent when retrieving response data an d releasing the lock by using the mbxget() command. the transaction id is generated internally by the processor and has no relationship to the originator of the request. on intel xeon processor e7-8800/4800/2800 product families processors, only a single outstanding transaction id is supported. therefore, it is recommended that all devices requesting actions or data from the mailbox complete their requests and release their semaphore in a timely manner. in order to accommodate future designs, software or hardware utilizing the peci mailbox must be capable of supporti ng transaction ids between 0 and 15. 6.3.2.9.3 releasing the mailbox the mailbox associated with a particular transaction id is only unlocked / released upon successful transmission of the last bit of the read fcs. if the originator aborts the transaction prior to transmission of this bit (presumably due to an fcs failure), the semaphore is maintained and the mbxget() command may be retried. 6.3.2.9.4 mailbox timeouts the mailbox is a shared resource that can result in artificial bandwidth conflicts among multiple querying processes that are shar ing the same originat or interface. the interface response time is quick, and with rare exception, back to back mbxsend() and mbxget() commands should result in successfu l execution of the request and release of the mailbox. in order to guarantee timely retrieval of response data and mailbox release, the mailbox semaphore has a timeout policy. if the peci bus has a cumulative ?0 time of 1ms since the semaphore was acquired, the semaphore is automatically cc: 0x85 failure due to lack of mailbox lock or invalid transaction id cc: 0x86 mailbox interface is unavailable or busy cc: 0xff unknown/invalid mailbox request table 6-13. mbxget() response definition response meaning
thermal specifications 138 datasheet volume 1 of 2 cleared. in the event that this timeout occu rs, the originating agent will receive a failed completion code upon issuing a mbxget() command, or even worse, it may receive corrupt data if this mbxget() command so happens to be interleaved with an mbxsend() from another pr ocess. please refer to ta b l e 6 - 1 3 for more information regarding failed completion codes from mbxget() commands. timeouts are undesirable, and the best way to avoid them and guarantee valid data is for the originating agent to always issu e mbxget() commands immediately following mbxsend() commands. alternately, mailbox timeout can be disabled. the bios may write msr misc_power_mgmt (0x1aa), bit 11 to 0b1 in order to force a disable of this automatic timeout. 6.3.2.9.5 response latency the peci mailbox interface is designed to have response data available within plenty of margin to allow for back-to-back mbxsend() and mbxget() requests. however, under rare circumstances that are out of the scope of this specification, it is possible that the response data is not available when the mbxget() command is issued. under these circumstances, the mbxget() command w ill respond with an abort fcs and the originator should re-issue the mbxget() request. 6.3.3 multi-domain commands the intel xeon processor e7-8800/4800/2800 product families processor does not support multiple domains, but it is possible that future products will, and the following tables are included as a reference for domain-specific definitions. 6.3.4 client responses 6.3.4.1 abort fcs the client responds with an abort fcs under the following conditions: ? the decoded command is not understood or not supported on this processor (this includes good command codes with bad read length or write length bytes). ? data is not ready. table 6-14. domain id definition domain id domain number 0b01 0 0b10 1 table 6-15. multi-domain command code reference command name domain 0 code domain 1 code gettemp() 0x01 0x02 pciconfigrd() 0xc1 0xc2 pciconfigwr() 0xc5 0xc6 mbxsend() 0xd1 0xd2 mbxget() 0xd5 0xd6
datasheet volume 1 of 2 139 thermal specifications ? assured write fcs (aw fcs) failure. note that under most circumstances, an assured write failure will appear as a bad fc s. however, when an originator issues a poorly formatted command with a miscalculated aw fcs, the client will intentionally abort the fcs in order to guarantee originator notification. 6.3.4.2 completion codes some peci commands respond with a completion code byte. these codes are designed to communicate the pass/fail status of the command and also provide more detailed information regarding the class of pass or fail. for all commands listed in section 6.3.2 that support completion codes, each command?s completion codes is listed in its respective section. what follows are some generalizations regarding completion codes. an originator that is decoding these commands can apply a simple mask to determine pass or fail. bit 7 is always set on a failed command, and is cleared on a passing command. note: the codes explicitly defined in this table may be useful in peci originator response algorithms. all reserved or undefined codes may be generated by a peci client device, and the originating agent must be capable of tolerating any code. the pass/fail mask defined in ta b l e 6 - 1 6 applies to all codes and general response policies may be based on that limited information. 6.3.5 originator responses the simplest policy that an originator may employ in response to receipt of a failing completion code is to retry the request. however, certain completion codes or fcs responses are indicative of an error in comm and encoding and a retry will not result in a different response from the client. furthermore, the message originator must have a response policy in the event of successive failure responses. table 6-16. completion code pass/fail mask 0xxx xxxxb command passed 1xxx xxxxb command failed table 6-17. device specific completion code (cc) definition completion code description 0x00..0x3f device specific pass code 0x40 command passed 0x4x command passed with a transaction id of ?x? (0x40 | transaction_id[3:0]) 0x50..0x7f device specific pass code cc: 0x80 error causing a response timeout. either due to a rare, internal timing condition or a processor reset condition or processor s1 state. retry is appropriate outside of the reset or s1 states. cc: 0x81 thermal configuration data was malformed or exceeded limits. cc: 0x82 thermal status mask is illegal cc: 0x83 invalid counter select cc: 0x84 invalid machine check bank or index cc: 0x85 failure due to lack of mailbox lock or invalid transaction id cc: 0x86 mailbox interface is unavailable or busy cc:0xff unknown/invalid mailbox request
thermal specifications 140 datasheet volume 1 of 2 refer to the definition of each command in section 6.3.2 for a specific definition of possible command codes or fcs responses for a given command. the following response policy definition is generic, and more advanced response policies may be employed at the discretion of the originator developer. 6.3.6 temperature data 6.3.6.1 format the temperature is formatted in a 16-bit, 2?s complement value representing a number of 1/64 degrees centigrade. this format allo ws temperatures in a range of 512c to be reported to approximately a 0.016c resolution. 6.3.6.2 interpretation the resolution of the processor?s digital thermal sensor (dts) is approximately 1c, which can be confirmed by a rdmsr from ia32_therm_status msr (0x19c) where it is architecturally defined. peci temperatures are sent through a configurable low-pass filter prior to delivery in the gettemp() respon se data. the output of this filter produces temperatures at the full 1/64c resolution even though the dts itself is not this accurate. temperature readings from the processor are always negative in a 2?s complement format, and imply an offset from the refe rence tcc activation temperature. as an example, assume that the tcc activation temperature reference is 100c. a peci thermal reading of -10 indicates that the processor is running approximately 10c below the tcc activation temperature, or 90c. peci temperature readings are not reliable at temperatures above tcc activation (since the processor is operating out of specification at this temperature). therefore, the readings are never positive. 6.3.6.3 temperature filtering the processor digital thermal sensor (dts) pr ovides an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals. coupled with the fact that typical fan speed controllers may only read temperatures at 4 hz, it is necessary for the thermal readings to reflect thermal table 6-18. originator response guidelines response after 1 attempt after 3 attempts bad fcs retry fail with peci client device error abort fcs retry fail with peci client device error. may be due to illegal command codes. cc: fail retry either the peci client doesn?t support the current command code, or it has failed in its attempts to construct a response. none (all 0?s) force bus idle (1ms low), retry fail with peci client device error. client may be dead or otherwise non- responsive (in reset or s1, for example). cc: pass pass n/a good fcs pass n/a figure 6-22. temperature sensor data format msb upper nibble msb lower nibble lsb upper nibble lsb lower nibble s x x x x x x x x x x x x x x x sign integer value (0-511) fractional value (~0.016)
datasheet volume 1 of 2 141 thermal specifications trends and not instantaneous readings. ther efore, peci supports a configurable low- pass temperature filtering function. by default, this filter results in a thermal reading that is a moving average of 256 samples ta ken at approximately 1msec intervals. this filter?s depth, or smoothing factor, may be configured to between 1 sample and 1024 samples, in powers of 2. see the follo wing equation for reference where the configurable variable is ?x?. t n = t n-1 + 1/2 x * (t sample - t n-1 ) refer to section 6.3.2.6.6 for the definition of the thermal configuration command. 6.3.6.4 reserved values several values well out of the operational range are reserved to signal temperature sensor errors. these are summarized in the following table: 6.3.7 client management 6.3.7.1 power-up sequencing the peci client is fully reset during proce ssor reset_n assertion. this means that any transactions on the bus will be completely ig nored, and the host will read the response from the client as all zeroes. after proc essor reset_n deassertion, the intel xeon processor e7-8800/4800/2800 product families processor peci client is operational enough to participate in timing negotiat ions and respond with reasonable data. however, the client data is not guaranteed to be fully populated until approximately 500 s after processor reset_n is deasserted . until that time, data may not be ready for all commands. note that peci commands may time out frequently during boot. the client responses to each command are as follows: in the event that the processor is tri-stated using power-on-configuration controls, the peci client will also be tri-stated. processor tri-state controls are described in chapter 7 . table 6-19. error codes and descriptions error code description 0x8000 general sensor error (gse) table 6-20. peci client re sponse during power-up (during ?data not ready?) command response ping() fully functional getdib() fully functional gettemp() client responds with a ?hot? reading, or 0x0000 pciconfigrd() fully functional pciconfigwr() fully functional mbxsend() fully functional mbxget() client responds with abort fcs (i f mbxsend() has been previously issued)
thermal specifications 142 datasheet volume 1 of 2 6.3.7.2 device discovery the peci client is available on all processo rs, and positive identification of the peci revision number can be achieved by issuing the getdib() command. please refer to section 6.3.2.2 for details on getdib response formatting. 6.3.7.3 client addressing the peci client assumes a default base address of 0x30. there are three skt_id# strapping pins that are used to strap each peci socket to a different node id (in addition to defining the processor's socket id). since skt_id# is active low, strapping a pin to ground results in value of 1 for that bit of the client id, and strapping to vio results in a value of 0 for that bit. the intel xeon processor 7500 series client addresses can therefore be strapped for va lues 0x30 through 0x37. these package pin straps are evaluated at the assertion of vccpwrgood. the client address may not be changed after vccpwrgood assertion, until the next power cycle on the processor. removal of a processor from its socket or tri-stating a processor in a mp configuration will have no impact to the remaining non-tri-stated peci client address. 6.3.7.4 c-states the intel xeon processor e7-8800/4800/2800 product families processor peci client is fully functional under all core and package c-states. support for package c-states is a function of processor sku and platform capabilities. because the intel xeon processor e7-8800/4800/2800 product families processor takes aggressive power savings actions under the deepest c-states, peci requests may have an impact to platform power. the impact is documented below: ? ping(), getdib(), gettemp() and mbxget() have no measurable impact on processor power under c-states. ? mbxsend(), pciconfigrd() and pciconfigwr() usage under package c-states may result in increased power consumption because the processor must temporarily return to a c0 state in order to execute the request. the exact power impact of a figure 6-23. peci power-up timeline bclk vio viopwrgd supplyvcc pwrgd cpureset# csi pins core execution c s i training id le running reset ucode boot bios peci client status dnr f u lly o p e ra tio n a l peci node id x n o d e id v alid
datasheet volume 1 of 2 143 thermal specifications pop-up to c0 varies by product sku, the c- state from which the pop-up is initiated, and the negotiated t bit . 6.3.7.5 s-states the peci client is always guaranteed to be operational under s0 and s1 sleep states. under s3 and deeper sleep states, the peci c lient response is undefined and, therefore, unreliable. 6.3.7.6 processor reset the intel xeon processor e7-8800/4800/2800 product families processor peci client is fully reset on all reset_n assertions. upon deassertion of reset_n, where power is maintained to the processor (otherwise kn own as a ?warm reset?), the following are true: ? the peci client assumes a bus idle state. ? the thermal filtering constant is retained. ? the gettemp() reading resets to 0x0000. ? any transaction in progress is aborted by the client (as measured by the client no longer participating in the response). ? the processor client is otherwise reset to a default configuration. table 6-21. power impact of peci commands vs. c-states command power impact ping() not measurable getdib() not measurable gettemp() not measurable pciconfigrd() requires a package ?pop-up? to a c0 state pciconfigwr() requires a package ?pop-up? to a c0 state mbxsend() requires a package ?pop-up? to a c0 state mbxget() not measurable table 6-22. peci client response during s1 command response ping() fully functional getdib() fully functional gettemp() fully functional pciconfigrd() fully functional pciconfigwr() fully functional mbxsend() fully functional mbxget() fully functional
thermal specifications 144 datasheet volume 1 of 2
datasheet volume 1 of 2 145 features 7 features 7.1 introduction the intel xeon processor e7-8800/4800/2800 product families processor package includes peci 2.0, tap and smbus interfaces which allow access to processor?s package information. the processor die is connected to the peci2.0 and tap, and these interfaces can be used for access to the configuration registers of the processor. the processor information rom (pirom) and scr atch eerom, are accessed via the smbus connection. note: actual implementation may vary. this figure is provided to offer a general understanding of the architecture. figure 7-1. logical schematic of intel ? xeon ? processor e7-8800/4800/2800 product families package vcc33 sm_wp xxthrmalert_n vcc a0 a2 scl sda xxspdclk xxspddat xxsktid[0] xxsktid[2] s2 s4 d2 d3 eeprom spdclk spddat sktid[0] smbclk smbdat package pins wp vcciof =1.1v thermalert_n a1 xxsktid[1] sktid[1] vcca vccb b1 b2 processor die sktid[2] s3 d4 s1 d1 gnd pca9509 gtl2003 sref gref gnd en 34c02 level shifter level shifter a2 a1 gnd
features 146 datasheet volume 1 of 2 7.2 clock control and low power states the processor supports low power states at the individual thread, core, and package level for optimal power management. 7.2.1 processor c-state power specifications ta b l e 7 - 1 lists c-state power specifications for various intel xeon processor e7-8800/ 4800/2800 product families processor skus. 7.3 sideband access to processor information rom via smbus 7.3.1 processor information rom table 7-1. processor c-state power specifications package c-state 1 notes: 1. values are with all cores in the specified c-state. intel xeon processor e7-8800/4800/2800 product families processor 130w intel xeon processor e7-8800/4800/2800 product families processor 105w intel xeon processor e7-8800/4800/2800 product families processor 95w c1e565454 c3 36 35 35 c6 31 29 29 offset/ section # of bits function notes examples header 00h 8 data format revision two 4-bit hex digits start with 00h 01-02h 16 pirom size size in bytes (msb first) use a decimal to hex transfer; 128 bytes = 0080h: 03h 8 processor data address byte pointer, 00h if not present 0eh 04h 8 processor core data address byt e pointer, 00h if not present 1bh 05h 8 processor uncore data address byte pointer, 00h if not present 2a 06h 8 package data address byte pointer, 00h if not present 4ch 07h 8 part number data address byt e pointer, 00h if not present 54h 08h 8 thermal reference data address byte pointer, 00h if not present 66h 09h 8 feature data address byte pointer, 00h if not present 6ch 0ah 8 other data address byte pointer, 00h if not present 77h 0b-0ch 16 reserved reserved for future use 0000h 0dh 8 checksum 1 byte checksum add up by byte and take 2?s complement processor data 0e-13h 48 s-spec number six 8-bit ascii characters 14h 7/1 sample/production first seven bits reserved 0b = sample, 1b = production 00000001 = production 15 6 2 number of cores number of threads [7:2] = number of cores [1:0] = threads per core 00100010 = 8 cores with 2 threads each 16-17h 16 system bus speed four 4-bit hex digits (mhz) 0133h = 133 mhz 1 18-19 16 reserved reserved for future use 0000h
datasheet volume 1 of 2 147 features 1ah 8 checksum 1 byte checksum add up by byte and take 2?s complement processor core data 1b-1ch 16 cpuid four 4-bit hex digits 1d-1eh 16 reserved reserved for future use 0000h 1f-20h 16 maximum p1 core frequency non-turbo boost (mhz) four 4-bit hex digits (mhz) 2000h = 2000 mhz 1 21-22h 16 maximum p0 core frequency turbo boost (mhz) four 4-bit hex digits (mhz) 2400h = 2400 mhz 1 23-24h 16 maximum core voltage id four 4-bit hex digits (mv) 1500h = 1500 mv 1 25-26h 16 minimum core voltage id four 4-bit hex digits (mv) 1000h = 1000 mv 1 27h 8 core voltage tolerance, high allowable positive dc shift two 4-bit hex digits (mv) 15h = 15mv 1 28h 8 core voltage tolerance, low allowable negative dc shift two 4-bit hex digits (mv) 15h = 15mv 1 29h 8 checksum 1 byte checksum add up by byte and take 2?s complement processor uncore data 2a-2bh 16 maximum intel qpi link transfer rate four 4-bit hex digits (in mt/s) 6400h = 6400 mt/s 1 5866h = 5866 mt/s 1 2c-2dh 16 minimum intel qpi link transfer rate four 4-bit hex digits (in mt/s) 4800h = 4800 mt/s 1 2e-31h 32 intel qpi version number four 8-bit ascii characters 01.0 32h 7/1 intel txt first seven bits reserved 00000001 = supported 00000000 = unsupported 33-34h 16 maximum intel smi transfer rate four 4-bit hex digits (in mt/s) 6400h = 6400 mt/s 1 5866h = 5866 mt/s 35-36h 16 minimum intel smi transfer rate four 4-bit hex digits (in mt/s) 4800h = 4800 mt/s 1 37-38h 16 vio voltage id four 4-bit hex digits (mv) 1125h = 1125 mv 1 39h 8 vio voltage tolerance, high edge finger tolerance two 4-bit hex digits (mv) 15h = 15 mv 1 3ah 8 vio voltage tolerance, low edge finger tolerance two 4-bit hex digits (mv) 15h = 15 mv 1 3b-3eh 32 reserved reserved for future use 00000000h 3f-40h 16 l2 cache size decimal (kb) per cpu core 0100h = 256 kb 41-42h 16 l3 cache size decimal (kb) 6000h = 24576 kb, 4800h = 18432 kb, 3000h = 12288 kb 43-44 16 cache voltage id four 4-bit hex digits (mv) 1500h = 1500 mv 1 45h 8 cache voltage tolerance, high allowable positive dc shift two 4-bit hex digits (mv) 15h = 15 mv 1 46h 8 cache voltage tolerance, lo w allowable negative dc shift two 4-bit hex digits (mv) 15h = 15 mv 1 47-4ah 32 reserved reserved for future use 00000000h 4bh 8 checksum 1 byte checksum add up by byte and take 2?s complement. package 4c-4fh 32 package revision four 8-bit ascii characters 01.0 50h 6/2 substrate revision software id first 6 bits reserved 000000** 51-52h 16 reserved reserved for future use 0000h 53h 8 checksum 1 byte checksum add up by byte and take 2?s complement. offset/ section # of bits function notes examples
features 148 datasheet volume 1 of 2 7.3.2 scratch eeprom also available in the memory component on the processor smbus is an eeprom which may be used for other data at the system or processor vendor?s discretion. the data in this eeprom, once programmed, can be writ e-protected by asserting the active-high sm_wp signal. this signal has a weak pull-down (10 k ) to allow the eeprom to be programmed in systems with no implementation of this signal. the scratch eeprom resides in the upper half of the memory component (addresses 80 - ffh). the lower half comprises the processor information rom (addresses 00 - 7fh), which is permanently write-protected by intel. part numbers 54-5ah 56 processor family number seven 8-bit ascii characters at80604 5b-62h 64 processor sku number seve n 8-bit ascii characters 003771aa 63-64h 16 reserved reserved for future use 0000h 65h 8 checksum 1 byte checksum add up by byte and take 2?s complement. thermal reference 66h 8 recommended thermalert_n assertion threshold value msb is reserved 0h = 0c 1 67h 8 thermal calibration offset value msb is reserved 0h = 0c 1 68h 8 t case maximum maximum case temperature two 4-bit hex digits (mv) 69h = 69c 1 69-6ah 16 thermal design power four 4-bit hex digits (in watts) 0130h = 130 watts 1 6bh 8 checksum 1 byte checksum add up by byte and take 2?s complement. features 6c-6fh 32 processor core feature flags from cpuid function 1, edx contents 4387fbffh 70h 8 processor feature flags eight features - binary 1 indicates functional feature 10001101 71h 8 additional processor feature flags eight additional features - binary 1 indicates functional feature 01110101 72 6/2 multiprocessor support 00b = up, 01b = dp, 10b = s2s, 11b = mp/sms 00000011 = mp/sms 73h 4/4 number of devices in tap chain first four bits reserved one 4-bit hex digit - bits *0h 1 74-75h 16 reserved reserved for future use 0000h 76h 8 checksum 1 byte checksum add up by byte and take 2?s complement. other 77-7eh 64 processor serial/electronic signature coded binary n/a 7fh 8 checksum 1 byte checksum add up by byte and take 2?s complement. notes: 1. uses binary coded decimal (bcd) translation. offset/ section # of bits function notes examples
datasheet volume 1 of 2 149 features 7.3.3 pirom and scratch eeprom supp orted smbus transactions the pirom responds to two smbus packet ty pes: read byte and write byte. however, since the pirom is write-protected, it will acknowledge a write byte command but ignore the data. the scratch eeprom re sponds to read byte and write byte commands. ta b l e 7 - 2 illustrates the read byte command. ta b l e 7 - 3 illustrates the write byte command. in the tables, ?s? represents a smbus start bit, ?p? represents a stop bit, ?a? represents an acknowledge (ack), and ?///? represen ts a negative acknowledge (nack). the shaded bits are transmitted by the pirom or scratch eeprom, and the bits that aren?t shaded are transmitted by the smbus host controller. in the tables, the data addresses indicate 8 bits. the smbus host controller should transmit 8 bits with the most significant bit indicating which section of the eeprom is to be addressed: the pirom (msb = 0) or the scratch eeprom (msb = 1). 7.4 smbus memory component addressing of the addresses broadcast across the smbus, the memory component claims those of the form ?10100xxzb?. the ?xx? bits are defined by pull-up and pull-down of the sktid[1:0] pins. note that sktid[2] does not affect the smbus address for the memory component. these address pins are pulled down weakly (10 k) on the processor substrate to ensure that the memory components are in a known state in systems which do not support the smbus (or only support a partial implementation). the ?z? bit is the read/write bit for the serial bus transaction. note that addresses of the form ?0000xxxxb? are reserved and should not be generated by an smbus master. ta b l e 7 - 4 describes the address pin connections and how they affect the addressing of the memory component. table 7-2. read byte smbus packet s slave address write a command code as slave address read a data /// p 17-bits 1 18-bits 117-bits 1 1 8-bits 1 1 table 7-3. write byte smbus packet s slave address write a command code adata ap 17-bits 1 18-bits 18-bits 11
features 150 datasheet volume 1 of 2 note: 1. this addressing scheme will support up to 4 processors on a single smbus. 7.5 managing data in the pirom the pirom consists of the following sections: ?header ? processor data ? processor core data ? processor uncore data ?cache data ?package data ? part number data ? thermal reference data ? feature data ? other data details on each of these sections are described below. note: reserved fields or bits should be progra mmed to zeros. however, oems should not rely on this model. 7.5.1 header to maintain backward compatibility, the head er defines the starting address for each subsequent section of the pirom. software should check for the offset before reading data from a particular section of the rom. example: code looking for the processor uncore data of a processor would read offset 05h to find a value of 29. 29 is the first address within the 'processor uncore data' section of the pirom. 7.5.1.1 dfr: data format revision this location identifies the data format revision of the pirom data structure. writes to this register have no effect. table 7-4. memory de vice smbus addressing address (hex) upper address 1 device select r/w bits 7-4 sktid[2] sktid[1] bit 2 sktid[0] bit 1 bit 0 a0h/a1h 10100 10100 0 0 x a2h/a3h 10100 10100 0 1 x a4h/a5h 10100 10100 1 0 x a6h/a7h 10100 10100 1 1 x
datasheet volume 1 of 2 151 features 7.5.1.2 pisize: pirom size this location identifies the pirom size. writes to this register have no effect. 7.5.1.3 pda: processor data address this location provides the offset to the processor data section. writes to this register have no effect. offset: 00h bit description 7:0 data format revision the data format revision is used wh enever fields within the pirom are redefined. the initial definition will begin at a value of 1. if a field, or bit assignment within a field, is changed such that software needs to discern between the old and new definition, then th e data format revision field will be incremented. 00h: reserved 01h: initial definition 02h: second revision 03h: third revision 04h: fourth revision 05h:fifth revision (defined by this document) 06h-ffh: reserved offset: 01h-02h bit description 15:0 pirom size the pirom size provides the size of the device in hex bytes. the msb is at location 01h; the lsb is at location 02h. 0000h - 007fh: reserved 0080h: 128 byte pirom size 0081- ffffh: reserved offset: 03h bit description 7:0 processor data address byte pointer to the processor data section 00h: processor data section not present 01h - 0dh: reserved 0eh: processor data section pointer value 0fh-ffh: reserved
features 152 datasheet volume 1 of 2 7.5.1.4 pcda: processor core data address this location provides the offset to the processor core data section. writes to this register have no effect. 7.5.1.5 puda: processor uncore data address this location provides the offset to the processor uncore data section. writes to this register have no effect. 7.5.1.6 pda: package data address this location provides the offset to the pack age data section. writes to this register have no effect. offset: 04h bit description 7:0 processor core data address byte pointer to the processor core data section 00h: processor core data section not present 01h - 09h: reserved 1ah: processor core data section pointer value 1bh-ffh: reserved offset: 05h bit description 7:0 processor uncore data address byte pointer to the processor uncore data section 00h: processor uncore data section not present 01h - 28h: reserved 29h: processor uncore data section pointer value 2ah-ffh: reserved offset: 06h bit description 7:0 package data address byte pointer to the package data section 00h: package data section not present 01h - 4ah: reserved 4bh: package data section pointer value 4ch-ffh: reserved
datasheet volume 1 of 2 153 features 7.5.1.7 pnda: part number data address this location provides the offset to the part number data section. writes to this register have no effect. 7.5.1.8 trda: thermal reference data address this location provides the offset to the thermal reference data section. writes to this register have no effect. 7.5.1.9 fda: feature data address this location provides the offset to the feature data section. writes to this register have no effect. offset: 07h bit description 7:0 part number data address byte pointer to the part number data section 00h: part number data section not present 01h - 52h: reserved 53h: part number data section poin ter value 54h-ffh: reserved offset: 08h bit description 7:0 thermal reference data address byte pointer to the thermal reference data section 00h: thermal reference data section not present 01h - 64h: reserved 65h: thermal reference data section pointer value 66h-ffh: reserved offset: 09h bit description 7:0 feature data address byte pointer to the feature data section 00h: feature data section not present 01h - 6ah: reserved 6bh: feature data section pointer value 6ch-ffh: reserved
features 154 datasheet volume 1 of 2 7.5.1.10 oda: other data address this location provides the offset to the other data section. writes to this register have no effect. 7.5.1.11 res1: reserved 1 this location is reserved. writes to this register have no effect. 7.5.1.12 hcks: header checksum this location provides the checksum of the he ader section. writes to this register have no effect. 7.5.2 processor data this section contains three pieces of data: ? the s-spec of the part in ascii format. ? (1) 2-bit field to declare if the part is a pre-production sample or a production unit. ? the system bus speed in bcd format 7.5.2.1 sqnum: s-spec number this location provides the s-spec number of the processor. the s-spec field is six ascii characters wide and is programmed with the same spec value as marked on the processor. if the value is less than six char acters in length, leading spaces (20h) are programmed in this field. writes to this register have no effect. offset: 0ah bit description 7:0 other data address byte pointer to the other data section 00h: other data section not present 01h - 78h: reserved 79h: other data sect ion pointer value 7ah- ffh: reserved offset: 0bh-0ch bit description 15:0 reserved 0000h-ffffh: reserved offset: 0dh bit description 7:0 header checksum one-byte checksum of the header section 00h- ffh: see section 7.5.10 for calculation of this value.
datasheet volume 1 of 2 155 features 7.5.2.2 samprod: sample/production this location contains the sample/production field, which is a two-bit field and is lsb aligned. all sample material will use a value of 00b. all s-spec material will use a value of 01b. all other values are reserved. writes to this register have no effect. example: a processor with an sxxxx mark (produ ction unit) will use 01h at offset 14h. 7.5.2.3 processor thread and core information this location contains information regarding the number of cores and threads on the processor. writes to this register have no effect. data format is binary. example : the intel xeon processor e7-8800/4800/2800 product families processor has up to 10 cores and two threads per core. offset: 0eh-13h bit description 47:40 character 6 s-spec or 20h 00h-0ffh: ascii character 39:32 character 5 s-spec or 20h 00h-0ffh: ascii character 31:24 character 4 s-spec character 00h-0ffh: ascii character 23:16 character 3 s-spec character 00h-0ffh: ascii character 15:8 character 2 s-spec character 00h-0ffh: ascii character 7:0 character 1 s-spec character 00h-0ffh: ascii character offset: 14h bit description 7:2 reserved 000000b-111111b: reserved 1:0 sample/production sample or production indictor 00b: sample 01b: production 10b-11b: reserved
features 156 datasheet volume 1 of 2 7.5.2.4 sbs: system bus speed this location contains the system bus fr equency information. systems may need to read this offset to decide if all installed processors support the same system bus speed. the data provided is the speed, rounded to a whole number, and reflected in binary coded decimal. writes to this register have no effect. example : a processor with system buss speed of 1.066ghz will have a value of 1066h. 7.5.2.5 res2: reserved 2 this location is reserved. writes to this register have no effect. 7.5.2.6 pdcks: processor data checksum this location provides the checksum of the processor data section. writes to this register have no effect. 7.5.3 processor core data this section contains silicon-related data relevant to the processor cores. 7.5.3.1 cpuid: cpuid this location contains the cpuid, processor type, family, model and stepping. the cpuid field is a copy of the results in eax[15:0] from function 1 of the cpuid instruction. writes to this register have no effect. data format is hexidecimal. offset: 15h bit description 7:2 number of cores 1:0 number of threads per core offset: 16h-17h bit description 15:0 system bus speed 0000h-ffffh: mhz offset: 18h-19h bit description 15:0 reserved 0000h-ffffh: reserved offset: 1ah bit description 7:0 processor data checksum one-byte checksum of the processor data section 00h- ffh: see section 7.5.10 for calculation of this value.
datasheet volume 1 of 2 157 features 7.5.3.2 res3: reserved 3 this locations are reserved. writes to this register have no effect. 7.5.3.3 mp1cf: maximum p1 core frequency this location contains the maximum non-turbo boost core frequency for the processor. the frequency should equate to the markings on the processor and/or the s-spec speed even if the parts are not limited or lo cked to the intended speed. format of this field is in mhz, rounded to a whole numb er, and encoded in binary coded decimal. writes to this register have no effect. example: a 2.666 ghz processor will have a value of 2666h. 7.5.3.4 mp0cf: maximum p0 core frequency this location contains the maximum turbo boost core frequency for the processor. this is the maximum intended speed for the part under any functional conditions. format of this field is in mhz, rounded to a whole number, and encoded in binary coded decimal. writes to this register have no effect. example: a processor with a maximum turbo b oost frequency of 2.666 ghz will have a value of 2666h. offset: 1bh-1ch bit description 15:13 reserved 00b-11b: reserved 12:12 processor type 0b-1b: processor type 11:8 processor family 0h-fh: processor family 7:4 processor model 0h-fh: processor model 3:0 processor stepping 0h-fh: processor stepping offset: 1dh-1eh bit description 15:0 reserved 0000h-ffffh: reserved offset: 1f-20h bit description 15:0 maximum p1 core frequency 0000h-ffffh: mhz
features 158 datasheet volume 1 of 2 7.5.3.5 maxvid: maximum core vid this location contains the maximum core vid (voltage identification) voltage that may be requested via the vid pins. this field, ro unded to the next thousandth, is in mv and is reflected in binary coded decimal. writes to this register have no effect. example: a voltage of 1.350 v maximum core vid would contain 1350h. 7.5.3.6 minvid: minimum core vid this location contains the minimum core vid (voltage identification) voltage that may be requested via the vid pins. this field, ro unded to the next thousandth, is in mv and is reflected in binary coded decimal. writes to this register have no effect. example: a voltage of 1.000 v maximum core vid would contain 1000h. 7.5.3.7 vth: core voltage tolerance, high this location contains the maximum core voltage tolerance dc offset high. this field, rounded to the next thousandth, is in mv and is reflected in binary coded decimal. writes to this register have no effect. a value of ff indicates that this value is undetermined. writes to this register have no effect. example: 50 mv tolerance would be saved as 50h. offset: 21h-22h bit description 15:0 maximum p0 core frequency 0000h-ffffh: mhz offset: 23h-24h bit description 15:0 maximum core vid 0000h-ffffh: mv offset: 25h-26h bit description 15:0 maximum core vid 0000h-ffffh: mv offset: 27h bit description 7:0 core voltage tolerance, high 00h-ffh: mv
datasheet volume 1 of 2 159 features 7.5.3.8 vtl: core voltage tolerance, low this location contains the maximum core voltage tolerance dc offset low. this field, rounded to the next thousandth, is in mv and is reflected in binary coded decimal. writes to this register have no effect. a value of ff indicates that this value is undetermined. writes to this register have no effect. example: 50 mv tolerance would be saved as 50h. 7.5.3.9 pdcks: processor core data checksum this location provides the checksum of the pr ocessor core data section. writes to this register have no effect. 7.5.4 processor uncore data this section contains silicon-related data relevant to the processor uncore. 7.5.4.1 maxqpi: maximum intel qpi transfer rate systems may need to read this offset to decide if all installed processors support the same intel qpi link transfer rate. the data provided is the transfer rate, rounded to a whole number, and reflected in binary coded de cimal. writes to this register have no effect. example: the intel xeon processor e7-8800/4800/2800 product families processor supports a maximum intel qpi link transfer ra te of 6.4 gt/s. therefore, offset 2ah-2bh has a value of 6400. 7.5.4.2 minqpi: minimum operat ing intel qpi transfer rate systems may need to read this offset to decide if all installed processors support the same intel qpi link transfer rate. this does not relate to the ?link power up? transfer rate of 1/4th ref clk. the data provided is the transfer rate, rounded to a whole number, and reflected in binary coded decimal. writes to this register have no effect. offset: 28h bit description 7:0 core voltage tolerance, low 00h-ffh: mv offset: 29h bit description 7:0 processor core data checksum one-byte checksum of the processor data section 00h- ffh: see section 7.5.10 for calculation of this value. offset: 2ah-2bh bit description 15:0 maximum intel qpi transfer rate 0000h-ffffh: mhz
features 160 datasheet volume 1 of 2 example : the intel xeon processor e7-8800/4800/2800 product families processor supports a minimum operating intel qpi link tran sfer rate of 4.8 gt/s. therefore, offset 2bh-2ch has a value of 4800. 7.5.4.3 qpivn: intel qpi version number the intel qpi version number is provided as four 8-bit ascii characters. writes to this register have no effect. example : the intel xeon processor e7-8800/4800/2800 product families processor supports intel qpi version number 1.0. ther efore, offset 2eh-31h has an ascii value of ?01.0?, which is 30, 31, 2e, 30. 7.5.4.4 txt: txt this location contains the txt location, which is a two-bit field and is lsb aligned. a value of 00b indicates txt is not supported. a value of 01b indicates txt is supported. writes to this register have no effect. example: a processor supporting txt will have offset 32h set to 01h. 7.5.4.5 maxsmi: maximum intel smi transfer rate systems may need to read this offset to decide on compatible processors and intel 7500 scalable memory buffer capabilities. th e data provided is the transfer rate, rounded to a whole number, and reflected in binary coded decimal. writes to this register have no effect. offset: 2ch-2dh bit description 15:0 minimum intel qpi transfer rate 0000h-ffffh: mhz offset: 2eh-31h bit description 31:0 intel qpi version number 00000000h-ffffffffh: mhz offset: 32h bit description 7:2 reserved 000000b-111111b: reserved 1:0 txt txt support indicator 00b: not supported 01b: supported 10b-11b: reserved
datasheet volume 1 of 2 161 features example : the intel xeon processor e7-8800/4800/2800 product families processor supports a maximum intel smi transfer rate of 6.4 gt/s. therefore, offset 33h-34h has a value of 6400h. 7.5.4.6 minsmi: minimum intel smi transfer rate this listing provides the minimum ?operating? intel smi transfer rate. systems may need to read this offset to decide if pr ocessors and intel 7500 scalable memory buffer s support the same intel smi transfer rate. the data provided is the transfer rate, rounded to a whole number, and reflected in binary coded decimal. writes to this register have no effect. example : the intel xeon processor e7-8800/4800/2800 product families processor supports a minimum operating intel smi transfer rate of 4.8 gt/s. therefore, offset 35h-36h has a hex value of 4800h. 7.5.4.7 viovid: vio vid offset 37h-38h is the processor vio vid (voltage identification) field and contains the voltage requested via the vid pins. this field, rounded to the next thousandth, is in mv and is reflected in binary coded decimal. some systems read this offset to determine if all processors support the same default vid setting. writes to this register have no effect. example: a voltage of 1.350 v maximum core vid would contain 1350h in offset 36- 37h. 7.5.4.8 viovth: vio voltage tolerance, high offset 39h contains the vio voltage tolerance, high. this is the maximum voltage swing above the required voltage allowed. th is field, rounded to the next thousandth, is in mv and is reflec ted in binary coded decimal. a value of ff indicates that this value is undetermined. writes to this register have no effect. example : a 50 mv tolerance would be saved as 50h. offset: 33h-34h bit description 15:0 maximum intel smi transfer rate 0000h-ffffh: mhz offset: 35h-36h bit description 15:0 minimum intel smi transfer rate 0000h-ffffh: mhz offset: 37h-38h bit description 15:0 vio vid 0000h-ffffh: mv
features 162 datasheet volume 1 of 2 7.5.4.9 viovtl: voltage tolerance, low offset 3ah contains the vio voltage toleranc e, low. this is the minimum voltage swing under the required voltage allowed. this field, rounded to the next thousandth, is in mv and is reflected in binary coded decimal. a value of ff indicates that this value is undetermined. writes to this register have no effect. example : a 50 mv tolerance would be saved as 50h. 7.5.4.10 res4: reserved 4 this location is reserved. writes to this register have no effect. 7.5.4.11 l2size: l2 cache size this location contains the size of the level-tw o cache in kilobytes. writes to this register have no effect. data format is decimal. example: the intel xeon processor e7-8800/4800/2800 product families processor has a 2.5 mb l2 cache. thus, offset 3fh-40h will contain a value of 0a00h. 7.5.4.12 l3size: l3 cache size this location contains the size of the leve l-three cache in kilobytes. writes to this register have no effect. data format is decimal. example: the intel xeon processor e7-8800/4800/2800 product families processor has up to a 30 mb l3 cache. thus, offset 41h-42h will contain a value of 8700h. offset: 39h bit description 7:0 vio voltage tolerance, high 00h-ffh: mv offset: 3ah bit description 7:0 core voltage tolerance, low 00h-ffh: mv offset: 3bh-3eh bit description 31:0 reserved 00000000h-ffffffffh: reserved offset: 3fh-40h bit description 15:0 l2 cache size 0000h-ffffh: kb
datasheet volume 1 of 2 163 features 7.5.4.13 cvid: cache voltage id this field contains the voltage requested via the cvid pins. this field is in mv and is reflected in hex. some systems read this offset to determine if all processors support the same default cvid setting. writes to this register have no effect. example: a voltage of 1.350 v cvid would contain an offset 43-44h value of 1350h. 7.5.4.14 cvth: cache voltage tolerance, high this location contains the maximum cache volt age tolerance dc offset high. this field, rounded to the next thousandth, is in mv an d is reflected in binary coded decimal. a value of ff indicates that this value is undetermined. writes to this register have no effect. example: a 50 mv tolerance would be saved as 50h. 7.5.4.15 cvtl: cache voltage tolerance, low this location contains the maximum cache voltage tolerance dc offset low. this field, rounded to the next thousandth, is in mv an d is reflected in binary coded decimal. a value of ff indicates that this value is undetermined. writes to this register have no effect. example: a 50 mv tolerance would be saved as 50h. offset: 41h-42h bit description 15:0 l3 cache size 0000h-ffffh: kb offset: 43h-44h bit description 15:0 cache voltage id 0000h-ffffh: mv offset: 45h bit description 7:0 cache voltage tolerance, high 00h-ffh: mv offset: 46h bit description 7:0 cache voltage tolerance, low 00h-ffh: mv
features 164 datasheet volume 1 of 2 7.5.4.16 res5: reserved 5 this location is reserved. writes to this register have no effect. 7.5.4.17 pudcks: processor uncore data checksum this location provides the checksum of the processor uncore data section. writes to this register have no effect. 7.5.5 package data this section contains substrate and other package related data. 7.5.5.1 prev: package revision this location tracks the highest level package revision. it is provided in an ascii format of four characters (8 bits x 4 characters = 32 bits). the package is documented as 1.0, 2.0, etc. if only three ascii characters ar e consumed, a leading space is provided in the data field. writes to this register have no effect. example : the intel xeon processor e7-8800/4800/2800 product families processor utilizes the first revision of the lga-1567 pack age. thus, at offset 4c-4f-35h, the data is a space followed by 1.0. in hex, this would be 20h, 31h, 2eh, 30h. offset: 47h-4ah bit description 31:0 reserved 00000000h-ffffffffh: reserved offset: 4bh bit description 7:0 processor uncore data checksum one-byte checksum of the processor uncore data section 00h- ffh: see section 7.5.10 for calculation of this value. offset: 4ch-4fh bit description 31:24 character 4 ascii character or 20h 00h-0ffh: ascii character 23:16 character 3 ascii character 00h-0ffh: ascii character 15:8 character 2 ascii character 00h-0ffh: ascii character 7:0 character 1 ascii character 00h-0ffh: ascii character
datasheet volume 1 of 2 165 features 7.5.5.2 substrate revision software id this location is a place holder for the substrate revision software id. writes to this register have no effect. 7.5.5.3 res6: reserved 6 this location is reserved. writes to this register have no effect. 7.5.5.4 pdcks: package data checksum this location provides the checksum of the pa ckage data section. writes to this register have no effect. 7.5.6 part number data this section provides device traceability. 7.5.6.1 pfn: processor family number this location contains seven ascii characters reflecting the intel? family number for the processor. this number is the same on all intel xeon processor e7-8800/4800/2800 product families processors. combined with the processor sku number below, this is the complete processor part number. this information is typically marked on the outside of the processor. if the part numbe r is less than 15 total characters, a leading space is inserted into the value. the part number should match the information found in the marking specification found in chapter 3 . writes to this register have no effect. example: a processor with a part number of at80604******** will have the following data found at offset 38-3eh: 41h, 54h, 38h, 30h, 36h, 30h, 34h. offset: 50h bit description 7:0 substrate revision software id 00h-ffh: reserved offset: 51h-52h bit description 15:0 reserved 0000h-ffffh: reserved offset: 53h bit description 7:0 package data checksum one-byte checksum of the package data section 00h- ffh: see section 7.5.10 for calculation of this value.
features 166 datasheet volume 1 of 2 7.5.6.2 psn: processor sku number this location contains eight ascii characters reflecting the intel? sku number for the processor. added to the end of the proce ssor family number above, this is the complete processor part number. this informat ion is typically marked on the outside of the processor. if the part number is less th an 15 total characters, a leading space is inserted into the value. the part number should match the information found in the marking specification found in chapter 3 . writes to this register have no effect. example: a processor with a part number of *******003771aa will have the following data found at offset 58-62h: 30h, 30h, 33h, 37h, 37h, 31h, 41h, 41h. offset: 54h-5ah bit description 55:48 character 7 ascii character or 20h 00h-0ffh: ascii character 47:40 character 6 ascii character or 20h 00h-0ffh: ascii character 39:32 character 5 ascii character or 20h 00h-0ffh: ascii character 31:24 character 4 ascii character 00h-0ffh: ascii character 23:16 character 3 ascii character 00h-0ffh: ascii character 15:8 character 2 ascii character 00h-0ffh: ascii character 7:0 character 1 ascii character 00h-0ffh: ascii character
datasheet volume 1 of 2 167 features 7.5.6.3 res7: reserved 7 this location is reserved. writes to this register have no effect. 7.5.6.4 pndcks: part number data checksum this location provides the checksum of the part number data section. writes to this register have no effect. offset: 5bh=62h bit description 63:56 character 8 00h-0ffh: ascii character 55:48 character 7 ascii character or 20h 00h-0ffh: ascii character 47:40 character 6 ascii character or 20h 00h-0ffh: ascii character 39:32 character 5 ascii character or 20h 00h-0ffh: ascii character 31:24 character 4 ascii character 00h-0ffh: ascii character 23:16 character 3 ascii character 00h-0ffh: ascii character 15:8 character 2 ascii character 00h-0ffh: ascii character 7:0 character 1 ascii character 00h-0ffh: ascii character offset: 63h-64h bit description 15:0 reserved 0000h-ffffh: reserved offset: 65h bit description 7:0 part number data checksum one-byte checksum of the part number data checksum 00h- ffh: see section 7.5.10 for calculation of this value.
features 168 datasheet volume 1 of 2 7.5.7 thermal reference data 7.5.7.1 tut: thermale rt upper threshold this location is a place holder for the thermalert upper threshold byte. writes to this register have no effect. 7.5.7.2 tco: thermal calibration offset this location is a place holder for the thermal calibration offset byte. writes to this register have no effect. 7.5.7.3 tcase: t case maximum this location provides the maximum t case for the processor. the field reflects temperature in degrees celsius in binary coded decimal format. this data can be found in chapter 6 . the thermal specifications are specified at the case integrated heat spreader (ihs). writes to this register have no effect. example: a temperature of 66c would contain a value of 66h. 7.5.7.4 tdp: thermal design power this location contains the maximum thermal design power for the part. the field reflects power in watts in binary coded decimal format. writes to this register have no effect. a zero value means that the value was not programmed. example: a 130w tdp would be saved as 0130h. offset: 66h bit description 7:0 thermalert upper threshold 0000h-ffffh: reserved offset: 67h bit description 7:0 thermal calibration offset 0000h-ffffh: reserved offset: 68h bit description 7:0 t case maximum 00h-ffh: degrees celsius offset: 69h-6ah bit description 15:0 thermal design power 0000h-ffffh: watts
datasheet volume 1 of 2 169 features 7.5.7.5 trdcks: thermal reference data checksum this location provides the checksum of the thermal reference data section. writes to this register have no effect. 7.5.8 feature data this section provides information on key features that the platform may need to understand without powering on the processor. 7.5.8.1 pcff: processor core feature flags this location contains a copy of results in edx[31:0] from function 1 of the cpuid instruction. these details provide instruct ion and feature support by product family. writes to this register have no effect. example: a value of bfebfbffh can be found at offset 6c - 6fh. 7.5.8.2 pff: processor feature flags this location contains additional feature information from the processor. writes to this register have no effect. note: bit 5 and bit 6 are mutually exclusive (only one bit will be set). bits are set when a feature is present, and cleared when they are not. offset: 6bh bit description 7:0 thermal reference data checksum one-byte checksum of the of thermal reference data checksum 00h- ffh: see section 7.5.10 for calculation of this value. offset: 6ch-6fh bit description 31:0 processor core feature flags 00000000h-fffffffff: feature flags offset: 70h bit description 7 multi-core (set if the processor is a multi-core processor) 6 serial signature (set if there is a serial signature at offset 5b- 62h) 5 electronic signature present (set if there is a electronic signature at 5b- 62h) 4 thermal sense device present (set if an smbus thermal sensor is on package) 3 reserved 2 oem eeprom present (set if there is a scratch rom at offset 80 - ffh) 1 core vid present (set if there is a vid provided by the processor) 0 l3 cache present (set if there is a level-3 cache on the processor)
features 170 datasheet volume 1 of 2 7.5.8.3 apff: additional processor feature flags this location contains additional feature info rmation from the processor. writes to this register have no effect. bits are set when a feature is present, and cleared when they are not. 7.5.8.4 mpsup: multiprocessor support this location contains 2 bits for representing the supported number of physical processors on the bus. these two bits are lsb aligned where 00b equates to non- scalable 2 socket (2s) operation, 01b to scalable 2 socket (s2s), 10 to scalable 4 socket (s4s), and scalable 8 socket (s8s). intel xeon processor e7-8800/4800/2800 product families processor is a s2s, s4s, or s8s processor. the first six bits in this field are reserved for future use. writes to this register have no effect. example: a scalable 8 socket processor will have a value of 03h at offset 71h. 7.5.8.5 tcdc: tap chain device count at offset 73, a 4-bit hex digit is used to tell how many devices are in the tap chain. because the intel xeon processor e7-8800/4800/2800 product families processor has ten cores, this field would be set to ah. offset: 71h bit description 7 reserved 6intel? cache safe technology 5 extended halt state (c1e) 4 intel? virtualization technology 3execute disable 2intel ? 64 1intel ? thermal monitor 2 0 enhanced intel speedstep ? technology offset: 72h bit description 7:2 reserved 000000b-111111b: reserved 1:0 multiprocessor support 2s, s2s, s4s or s8s indicator 00b: non-scalable 2 socket 01b: scalable 2 socket 10b: scalable 4 socket 11b: scalable 8 socket
datasheet volume 1 of 2 171 features 7.5.8.6 res9: reserved 9 this location is reserved. writes to this register have no effect. 7.5.8.7 trdcks: thermal reference data checksum this location provides the checksum of the thermal reference data section. writes to this register have no effect. 7.5.9 other data this section contains a large reserved area , and items added after the original format for the intel xeon processor e7-8800/4800/2800 product families processor pirom was set. 7.5.9.1 ps/esig: processor se rial/electronic signature this location contains a 64-bit identification number. the value in this field is either a serial signature or an electronic signature. writes to this register have no effect. offset: 73h bit description 7:0 tap chain device count 0000h-ffffh: reserved offset: 74h-75h bit description 15:0 reserved 0000h-ffffh: reserved offset: 76h bit description 7:0 thermal reference data checksum one-byte checksum of the thermal reference data checksum 00h- ffh: see section 7.5.10 for calculation of this value. offset: 77h-7eh bit description 63:0 processor serial/electronic signature 0000000000000000h-ffffffffffffffffh: electronic signature
features 172 datasheet volume 1 of 2 7.5.9.2 odcks: other data checksum this location provides the checksum for the other data section. writes to this register have no effect. 7.5.10 checksums the pirom includes multiple checksums. ta b l e 7 - 5 includes the checksum values for each section defined in the 128-byte rom. checksums are automatically calculated and programmed by intel?. the first step in calculating the checksum is to add each byte from the field to the next subsequent byte. this result is then negated to provide the checksum. example: for a byte string of aa445ch, th e resulting checksum will be b6h. aa = 10101010 44 = 01000100 5c = 0101100 aa + 44 + 5c = 01001010 negate the sum: 10110101 +1 = 101101 (b6h) offset: 7fh bit description 7:0 other data checksum one-byte checksum of the other data checksum 00h- ffh: see section 7.5.10 for calculation of this value. table 7-5. 128-byte rom checksum values section checksum address header 0dh processor data 1ah processor core data 29h processor uncore data 4bh package data 53h part number data 65h feature data 76h other data 7fh
datasheet volume 1 of 2 173 debug tools specifications 8 debug tools specifications for debug purposes, the socket ls pin definition has allocated signals to install a logic analyzer probe head to observe intel qpi traffic. 8.1 logic analyzer interface due to the complexity of intel xeon pr ocessor e7-8800/4800/2800 product families processor-based multiprocessor systems, the logic analyzer interface (lai) is critical in providing the ability to probe and capture hi gh-speed signals. there are two sets of considerations to keep in mind when designing a intel xeon processor e7-8800/4800/ 2800 product families processor-based system that can make use of an lai: mechanical and electrical. 8.1.1 mechanical considerations the lai is installed between the processor socket and the processor. the lai pins plug into the socket, while the processor pins plug into a socket on the lai. cabling that is part of the lai egresses the system to allow an electrical connection between the processor and a logic analyzer. the maximum volume occupied by the lai, known as the keepout volume, as well as the cable egre ss restrictions, should be obtained from the logic analyzer vendor. system designers must make sure that the keepout volume remains unobstructed inside the system. note that it is possible that the keepout volume reserved for the lai may differ from the space normally occupied by the intel xeon processor e7-8800/4800/2800 product fami lies processor heatsink. if this is the case, the logic analyzer vendor will provide a cooling solution as part of the lai. 8.1.2 electrical considerations instrumented intel qpi links will require eq ualization settings unique for that topology. the platform will need to load updated opti mized equalization settings for instrumented links. the method of obtaining the new set of e.q settings is via the signal integrity support tools for advanced interfaces (sistai) tools, following the same procedures.
debug tools specifications 174 datasheet volume 1 of 2

▲Up To Search▲

Price & Availability of 325119-001

	To Download 325119-001 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .